colormap.vhd

VHDL语言按VGA接口标准把数字图像信号转换成标准VGA格式。适合做学习试验

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity colormap is
    Port ( hloc : in std_logic_vector(9 downto 0);
           vloc : in std_logic_vector(9 downto 0);
           rgbx : out std_logic_vector(2 downto 0);
           rgby : out std_logic_vector(2 downto 0));
end colormap;

architecture Behavioral of colormap is

begin
  process(hloc,vloc)
  begin
     case hloc(7 downto 5) is
	    when "000" => rgbx <= "100";
		 when "001" => rgbx <= "110";
		 when "010" => rgbx <= "101";
		 when "011" => rgbx <= "010";
		 when "100" => rgbx <= "001";
		 when "101" => rgbx <= "011";
		 when "110" => rgbx <= "111";
		 when "111" => rgbx <= "000";
		 when others => rgbx <= "000";
	  end case;
	  case vloc(7 downto 5) is
	    when "000" => rgby <= "100";
		 when "001" => rgby <= "110";
		 when "010" => rgby <= "101";
		 when "011" => rgby <= "010";
		 when "100" => rgby <= "001";
		 when "101" => rgby <= "011";
		 when "110" => rgby <= "111";
		 when "111" => rgby <= "000";
		 when others => rgby <= "000";
	  end case;
  end process;
end Behavioral;