qsine6.tdf

Vhdl实现计算exp功能 在apex20k上经过验证

subdesign qsine6
(
        angle[5..0]             :       input;
        out[7..0]               :       output;
)
begin
case angle[] is
when 0 =>
out[]=0;
when 1 =>
out[]=3;
when 2 =>
out[]=6;
when 3 =>
out[]=9;
when 4 =>
out[]=13;
when 5 =>
out[]=16;
when 6 =>
out[]=19;
when 7 =>
out[]=22;
when 8 =>
out[]=25;
when 9 =>
out[]=28;
when 10 =>
out[]=31;
when 11 =>
out[]=34;
when 12 =>
out[]=37;
when 13 =>
out[]=40;
when 14 =>
out[]=43;
when 15 =>
out[]=46;
when 16 =>
out[]=49;
when 17 =>
out[]=52;
when 18 =>
out[]=55;
when 19 =>
out[]=58;
when 20 =>
out[]=61;
when 21 =>
out[]=63;
when 22 =>
out[]=66;
when 23 =>
out[]=69;
when 24 =>
out[]=72;
when 25 =>
out[]=74;
when 26 =>
out[]=77;
when 27 =>
out[]=79;
when 28 =>
out[]=82;
when 29 =>
out[]=84;
when 30 =>
out[]=86;
when 31 =>
out[]=89;
when 32 =>
out[]=91;
when 33 =>
out[]=93;
when 34 =>
out[]=95;
when 35 =>
out[]=97;
when 36 =>
out[]=99;
when 37 =>
out[]=101;
when 38 =>
out[]=103;
when 39 =>
out[]=105;
when 40 =>
out[]=107;
when 41 =>
out[]=108;
when 42 =>
out[]=110;
when 43 =>
out[]=112;
when 44 =>
out[]=113;
when 45 =>
out[]=114;
when 46 =>
out[]=116;
when 47 =>
out[]=117;
when 48 =>
out[]=118;
when 49 =>
out[]=119;
when 50 =>
out[]=120;
when 51 =>
out[]=121;
when 52 =>
out[]=122;
when 53 =>
out[]=123;
when 54 =>
out[]=124;
when 55 =>
out[]=124;
when 56 =>
out[]=125;
when 57 =>
out[]=126;
when 58 =>
out[]=126;
when 59 =>
out[]=126;
when 60 =>
out[]=127;
when 61 =>
out[]=127;
when 62 =>
out[]=127;
when 63 =>
out[]=127;
end case;
end;