sine.tdf

来自「Vhdl实现计算exp功能 在apex20k上经过验证」· TDF 代码 · 共 26 行

subdesign sine
(
        angle[7..0]                             :       input;
        clock                                   :       input;
        sine[7..0]                              :       output;
)
variable
        reg[7..0]                               :       dff;
        fn_sine1                                :       qsine6;
        fn_sine2                                :       qsine6;
begin
        sine[]=reg[];
        reg[].clk=clock;
        fn_sine1.angle[]=angle[5..0];
        fn_sine2.angle[]=63-angle[5..0];
        case angle[7..6] is
                when 0 =>
                        reg[]=fn_sine1.out[];
                when 1 =>
                        reg[]=fn_sine2.out[];
                when 2 =>
                        reg[]=-fn_sine1.out[];
                when 3 =>
                        reg[]=-fn_sine2.out[];
        end case;
end;