file.v

来自「该文件用在CPLD上的」· Verilog 代码 · 共 13 行

// file
module top(clkin,clear,sum);
output [4:0] sum;
input clkin,clear;
reg [4:0] sum;

  always @(posedge clkin or negedge clear)
     if(!clear)
        sum = 0;
     else
        sum = sum + 1;

endmodule