pn_code.npl

系数为4的扰码生成器

JDF G
// Created by Project Navigator ver 1.0
PROJECT pn_code
DESIGN pn_code
DEVFAM spartan2
DEVFAMTIME 0
DEVICE xc2s50
DEVICETIME 0
DEVPKG tq144
DEVPKGTIME 0
DEVSPEED -6
DEVSPEEDTIME 0
DEVTOPLEVELMODULETYPE HDL
TOPLEVELMODULETYPETIME 0
DEVSYNTHESISTOOL XST (VHDL/Verilog)
SYNTHESISTOOLTIME 0
DEVSIMULATOR Modelsim
SIMULATORTIME 0
DEVGENERATEDSIMULATIONMODEL VHDL
GENERATEDSIMULATIONMODELTIME 0
SOURCE pn_code.v
STIMULUS pn_code_test.v
[STRATEGY-LIST]
Normal=True