sja1000p.c

PCM9880是一块PC/104界面的双端口隔离CAN总线通讯卡

/* sja1000.c
 * Linux CAN-bus device driver.
 * Written by Arnaud Westenberg email:[e-mail]
 * This software is released under the GPL-License.
 * Version 0.6 18 Sept 2000
 * Changed for PeliCan mode SJA1000 by Tomasz Motylewski (BFAD GmbH)
 * [e-mail]
 */

#include <linux/autoconf.h>
#if defined (CONFIG_MODVERSIONS) && !defined (MODVERSIONS)
#define MODVERSIONS
#endif

#if defined (MODVERSIONS)
#include <linux/modversions.h>
#endif

#include <linux/sched.h>
#include <linux/delay.h>
#include <asm/irq.h>

#include "../include/main.h"
#include "../include/sja1000p.h"

struct chip_t *chip_irq=NULL;
struct candevice_t *device_irq=NULL;
struct canfifo_t *fifo_irq=NULL;
void (*put_reg)(unsigned char data, unsigned long address);
unsigned (*get_reg)(unsigned long address);



int sja1000p_enable_configuration(struct chip_t *chip)
{
	int i=0;
	enum sja1000_PeliCAN_MOD flags;

	disable_irq(chip->chip_irq);

	flags=can_read_reg(chip,SJAMOD);

	while ((!(flags & MOD_RM)) && (i<=10)) {
		can_write_reg(chip, MOD_RM, SJAMOD);
// TODO: chinfigurable MOD_AFM (32/16 bit acceptance filter)
// config MOD_LOM (listen only)
		udelay(100);
		i++;
		flags=can_read_reg(chip, SJAMOD);
	}
	if (i>=10) {
		CANMSG("Reset error\n");
		enable_irq(chip->chip_irq);
		return -ENODEV;
	}

	return 0;
}

int sja1000p_disable_configuration(struct chip_t *chip)
{
	int i=0;
	enum sja1000_PeliCAN_MOD flags;

	flags=can_read_reg(chip,SJAMOD);

	while ( (flags & MOD_RM) && (i<=10) ) {
		can_write_reg(chip, 0, SJAMOD);
// TODO: chinfigurable MOD_AFM (32/16 bit acceptance filter)
// config MOD_LOM (listen only)
		udelay(100);
		i++;
		flags=can_read_reg(chip, SJAMOD);
	}
	if (i>=10) {
		CANMSG("Error leaving reset status\n");
		return -ENODEV;
	}

	enable_irq(chip->chip_irq);

	return 0;
}

int sja1000p_chip_config(struct chip_t *chip)
{
	if (sja1000p_enable_configuration(chip))
		return -ENODEV;

	/* Set mode, clock out, comparator */
	can_write_reg(chip,CDR_PELICAN|chip->sja_cdr_reg,SJACDR); 
	/* Set driver output configuration */
	can_write_reg(chip,chip->sja_ocr_reg,SJAOCR); 

	if (sja1000p_extended_mask(chip,0x00000000, 0xffffffff))
		return -ENODEV;
	
	if (!baudrate)
		baudrate=1000;
	if (sja1000p_baud_rate(chip,1000*baudrate,chip->clock,0,75,0))
		return -ENODEV;

	/* Enable hardware interrupts */
	can_write_reg(chip, ENABLE_INTERRUPTS, SJAIER); 

	sja1000p_disable_configuration(chip);
	
	return 0;
}

int sja1000p_extended_mask(struct chip_t *chip, unsigned long code, unsigned  long mask)
{
	int i;

	if (sja1000p_enable_configuration(chip))
		return -ENODEV;

// LSB to +3, MSB to +0	
	for(i=SJA_PeliCAN_AC_LEN; --i>=0;) {
		can_write_reg(chip,code&0xff,SJAACR0+i);
		can_write_reg(chip,mask&0xff,SJAAMR0+i);
		code >>= 8;
		mask >>= 8;
	}

	DEBUGMSG("Setting acceptance code to 0x%lx\n",(unsigned long)code);
	DEBUGMSG("Setting acceptance mask to 0x%lx\n",(unsigned long)mask);

	sja1000p_disable_configuration(chip);

	return 0;
}

/* Set communication parameters.
 * param rate baud rate in Hz
 * param clock frequency of sja1000 clock in Hz (ISA osc is 14318000)
 * param sjw synchronization jump width (0-3) prescaled clock cycles
 * param sampl_pt sample point in % (0-100) sets (TSEG1+1)/(TSEG1+TSEG2+2) ratio
 * param flags fields BTR1_SAM, OCMODE, OCPOL, OCTP, OCTN, CLK_OFF, CBP
 */
int sja1000p_baud_rate(struct chip_t *chip, int rate, int clock, int sjw,
							int sampl_pt, int flags)
{
	int best_error = 1000000000, error;
	int best_tseg=0, best_brp=0, best_rate=0, brp=0;
	int tseg=0, tseg1=0, tseg2=0;
	
	if (sja1000p_enable_configuration(chip))
		return -ENODEV;

	clock /=2;

	/* tseg even = round down, odd = round up */
	for (tseg=(0+0+2)*2; tseg<=(MAX_TSEG2+MAX_TSEG1+2)*2+1; tseg++) {
		brp = clock/((1+tseg/2)*rate)+tseg%2;
		if (brp == 0 || brp > 64)
			continue;
		error = rate - clock/(brp*(1+tseg/2));
		if (error < 0)
			error = -error;
		if (error <= best_error) {
			best_error = error;
			best_tseg = tseg/2;
			best_brp = brp-1;
			best_rate = clock/(brp*(1+tseg/2));
		}
	}
	if (best_error && (rate/best_error < 10)) {
		CANMSG("baud rate %d is not possible with %d Hz clock\n",
								rate, 2*clock);
		CANMSG("%d bps. brp=%d, best_tseg=%d, tseg1=%d, tseg2=%d\n",
				best_rate, best_brp, best_tseg, tseg1, tseg2);
		return -EINVAL;
	}
	tseg2 = best_tseg-(sampl_pt*(best_tseg+1))/100;
	if (tseg2 < 0)
		tseg2 = 0;
	if (tseg2 > MAX_TSEG2)
		tseg2 = MAX_TSEG2;
	tseg1 = best_tseg-tseg2-2;
	if (tseg1>MAX_TSEG1) {
		tseg1 = MAX_TSEG1;
		tseg2 = best_tseg-tseg1-2;
	}

	DEBUGMSG("Setting %d bps.\n", best_rate);
	DEBUGMSG("brp=%d, best_tseg=%d, tseg1=%d, tseg2=%d, sampl_pt=%d\n",
					best_brp, best_tseg, tseg1, tseg2,
					(100*(best_tseg-tseg2)/(best_tseg+1)));


	can_write_reg(chip, sjw<<6 | best_brp, SJABTR0);
	can_write_reg(chip, ((flags & BTR1_SAM) != 0)<<7 | (tseg2<<4) 
					| tseg1, SJABTR1);

	sja1000p_disable_configuration(chip);

	return 0;
}

void sja1000p_read(struct chip_t *chip, struct canfifo_t *fifo) {
	int i, flags, len, datastart;
	do {
		flags = can_read_reg(chip,SJAFRM);
		if(flags&FRM_FF) {
			fifo->buf_rx_entry[fifo->head].id =
				(can_read_reg(chip,SJAID0)<<21) +
				(can_read_reg(chip,SJAID1)<<13) +
				(can_read_reg(chip,SJAID2)<<5) +
				(can_read_reg(chip,SJAID3)>>3);
			datastart = SJADATE;
		} else {
			fifo->buf_rx_entry[fifo->head].id =
				(can_read_reg(chip,SJAID0)<<3) +
				(can_read_reg(chip,SJAID1)>>5);
			datastart = SJADATS;
		}
		fifo->buf_rx_entry[fifo->head].flags =
			((flags & FRM_RTR) ? MSG_RTR : 0) |
			((flags & FRM_FF) ? MSG_EXT : 0);
		len = flags & FRM_DLC_M;
		for(i=0; i< len; i++) {
			fifo->buf_rx_entry[fifo->head].data[i]=
				can_read_reg(chip,datastart+i);
		}
		fifo->buf_rx_entry[fifo->head].length = len;
		fifo->head++; fifo->head %= MAX_BUF_LENGTH;
// FIXME: what if fifo->head == fifo->tail again ?
		can_write_reg(chip, CMR_RRB, SJACMR);
	} while (can_read_reg(chip, SJASR) & SR_RBS);
}

int sja1000p_pre_read_config(struct chip_t *chip, struct msgobj_t *obj)
{
	int i;
	i=can_read_reg(chip,SJASR);
	
	if (!(i&SR_RBS)) {
		return 0;
	}

	can_write_reg(chip, DISABLE_INTERRUPTS, SJAIER); //disable interrupts for a moment
	sja1000p_read(chip, obj->fifo);
	can_write_reg(chip, ENABLE_INTERRUPTS, SJAIER); //enable interrupts
	return 1;
}

#define MAX_TRANSMIT_WAIT_LOOPS 200
int sja1000p_pre_write_config(struct chip_t *chip, struct msgobj_t *obj, 
							struct canmsg_t *msg)
{
	int i=0; 
	unsigned int id;

	/* Wait until Transmit Buffer Status is released */
	while ( !(can_read_reg(chip, SJASR) & SR_TBS) && 
						i++<MAX_TRANSMIT_WAIT_LOOPS) {
		udelay(i);
	}
	
	if (!(can_read_reg(chip, SJASR) & SR_TBS)) {
		CANMSG("Transmit timed out, cancelling\n");
// here we should check if there is no write/select waiting for this
// transmit. If so, set error ret and wake up.
// CHECKME: if we do not disable IER_TIE (TX IRQ) here we get interrupt
// immediately
		can_write_reg(chip, CMR_AT, SJACMR);
		i=0;
		while ( !(can_read_reg(chip, SJASR) & SR_TBS) &&
						i++<MAX_TRANSMIT_WAIT_LOOPS) {
			udelay(i);
		}
		if (!(can_read_reg(chip, SJASR) & SR_TBS)) {
			CANMSG("Could not cancel, please reset\n");
			return -EIO;
		}
	}
	msg->length &= FRM_DLC_M;
	can_write_reg(chip, ((msg->flags&MSG_EXT)?FRM_FF:0) |
		((msg->flags & MSG_RTR) ? FRM_RTR : 0) |
		msg->length, SJAFRM);
	if(msg->flags&MSG_EXT) {
		id=msg->id<<3;
		can_write_reg(chip, id & 0xff, SJAID3);
		id >>= 8;
		can_write_reg(chip, id & 0xff, SJAID2);
		id >>= 8;
		can_write_reg(chip, id & 0xff, SJAID1);
		id >>= 8;
		can_write_reg(chip, id, SJAID0);
		for(i=0; i < msg->length; i++) {
			can_write_reg(chip, msg->data[i], SJADATE+i);
		}
	} else {
		id=msg->id >> 5;
		can_write_reg(chip, id & 0xff, SJAID0);
		id >>= 8;
		can_write_reg(chip, id & 0xff, SJAID1);
		for(i=0; i < msg->length; i++) {
			can_write_reg(chip, msg->data[i], SJADATS+i);
		}
	}
	return 0;
}

int sja1000p_send_msg(struct chip_t *chip, struct msgobj_t *obj, 
							struct canmsg_t *msg)
{
	can_write_reg(chip, CMR_TR, SJACMR);

	return 0;
}

int sja1000p_check_tx_stat(struct chip_t *chip)
{
	if (can_read_reg(chip,SJASR) & SR_TCS)
		return 0;
	else
		return 1;
}

int sja1000p_set_btregs(struct chip_t *chip, unsigned short btr0, 
							unsigned short btr1)
{
	if (sja1000p_enable_configuration(chip))
		return -ENODEV;

	can_write_reg(chip, btr0, SJABTR0);
	can_write_reg(chip, btr1, SJABTR1);

	sja1000p_disable_configuration(chip);

	return 0;
}

int sja1000p_start_chip(struct chip_t *chip)
{
	enum sja1000_PeliCAN_MOD flags;

	flags = can_read_reg(chip, SJAMOD) & (MOD_LOM|MOD_STM|MOD_AFM|MOD_SM);
	can_write_reg(chip, flags, SJAMOD);

	return 0;
}

int sja1000p_stop_chip(struct chip_t *chip)
{
	enum sja1000_PeliCAN_MOD flags;

	flags = can_read_reg(chip, SJAMOD) & (MOD_LOM|MOD_STM|MOD_AFM|MOD_SM);
	can_write_reg(chip, flags|MOD_RM, SJAMOD);

	return 0;
}


int sja1000p_remote_request(struct chip_t *chip, struct msgobj_t *obj)
{
	CANMSG("sja1000p_remote_request not implemented\n");
	return -ENOSYS;
}

int sja1000p_standard_mask(struct chip_t *chip, unsigned short code,
		unsigned short mask)
{
	CANMSG("sja1000p_standard_mask not implemented\n");
	return -ENOSYS;
}

int sja1000p_clear_objects(struct chip_t *chip)
{
	CANMSG("sja1000p_clear_objects not implemented\n");
	return -ENOSYS;
}

int sja1000p_config_irqs(struct chip_t *chip, short irqs)
{
	CANMSG("sja1000p_config_irqs not implemented\n");
	return -ENOSYS;
}

void sja1000p_irq_handler(int irq, void *dev_id, struct pt_regs *regs)
{
	int irq_register;
	chip_irq=(struct chip_t *)dev_id;
	device_irq=(struct candevice_t *)chip_irq->hostdevice;

	put_reg=device_irq->hwspecops->write_register;
	get_reg=device_irq->hwspecops->read_register;

	irq_register=get_reg(chip_irq->chip_base_addr+SJAIR);
//	DEBUGMSG("sja1000_irq_handler: SJAIR:%02x\n",irq_register);
//	DEBUGMSG("sja1000_irq_handler: SJASR:%02x\n",
//					get_reg(chip_irq->chip_base_addr+SJASR));

	if ((irq_register & (IR_BEI|IR_EPI|IR_DOI|IR_EI|IR_TI|IR_RI)) == 0)
		return;

	fifo_irq=chip_irq->msgobj[0]->fifo;

	if ((irq_register & IR_RI) != 0) {
		sja1000p_read(chip_irq,fifo_irq);
		chip_irq->msgobj[0]->ret = 0;
		if (waitqueue_active(&fifo_irq->readq))
			wake_up_interruptible(&fifo_irq->readq);
	}
	if ((irq_register & IR_TI) != 0) {
		chip_irq->msgobj[0]->ret = 0;
		if (waitqueue_active(&fifo_irq->writeq))
			wake_up_interruptible(&fifo_irq->writeq);
	}
	if ((irq_register & (IR_EI|IR_BEI|IR_EPI|IR_DOI)) != 0) { 
		// Some error happened
		CANMSG("Error: status register: 0x%x irq_register: 0x%02x\n",
			get_reg(chip_irq->chip_base_addr+SJASR), irq_register);
// FIXME: chip should be brought to usable state. Transmission cancelled if in progress.
// Reset flag set to 0 if chip is already off the bus. Full state report
		chip_irq->msgobj[0]->ret=-1;
		if (waitqueue_active(&fifo_irq->writeq))
			wake_up_interruptible(&fifo_irq->writeq);
		if (waitqueue_active(&fifo_irq->readq))
			wake_up_interruptible(&fifo_irq->readq);
	}

	return;
}

int sja1000p_register(struct chipspecops_t *chipspecops)
{
	CANMSG("initializing sja1000p chip operations\n");
	chipspecops->chip_config=sja1000p_chip_config;
	chipspecops->baud_rate=sja1000p_baud_rate;
	chipspecops->standard_mask=sja1000p_standard_mask;
	chipspecops->extended_mask=sja1000p_extended_mask;
	chipspecops->message15_mask=sja1000p_extended_mask;
	chipspecops->clear_objects=sja1000p_clear_objects;
	chipspecops->config_irqs=sja1000p_config_irqs;
	chipspecops->pre_read_config=sja1000p_pre_read_config;
	chipspecops->pre_write_config=sja1000p_pre_write_config;
	chipspecops->send_msg=sja1000p_send_msg;
	chipspecops->check_tx_stat=sja1000p_check_tx_stat;
	chipspecops->remote_request=sja1000p_remote_request;
	chipspecops->enable_configuration=sja1000p_enable_configuration;
	chipspecops->disable_configuration=sja1000p_disable_configuration;
	chipspecops->set_btregs=sja1000p_set_btregs;
	chipspecops->start_chip=sja1000p_start_chip;
	chipspecops->stop_chip=sja1000p_stop_chip;
	chipspecops->irq_handler=sja1000p_irq_handler;
	return 0;
}