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本人初学VHDL时编的比较系统的VHDL源程序 巨实用

library IEEE;
use IEEE.std_logic_1164.all;

entity encomp is
    port (
        a: in STD_LOGIC_VECTOR (3 downto 0);
        b: in STD_LOGIC_VECTOR (3 downto 0);
        equals: out STD_LOGIC
    );
end encomp;

architecture encomp_arch of encomp is
begin
  equals<='1' when(a=b) else '0';
end encomp_arch;