本人初学VHDL时编的比较系统的VHDL源程序 巨实用

library IEEE;
use IEEE.std_logic_1164.all;

entity addr_8 is
    port (
        
        a: in STD_LOGIC_VECTOR (7 downto 0);
        b: in STD_LOGIC_VECTOR (7 downto 0);
        sum: out STD_LOGIC_VECTOR (7 downto 0);
        co: out STD_LOGIC
    );
end addr_8;

architecture addr_8_arch of addr_8 is
component adder 
	port ( ci :in std_logic ;
	a ,b : in std_logic ;
	sum ,co : out std_logic );
	end component ;
component halfadd 
	port ( 
	a ,b : in std_logic ;
	c ,co : out std_logic );
	end component ;
	
	signal c: std_logic_vector ( 7 downto 1 );
	
begin

	u1 : halfadd port map (a(0),b(0),sum (0),c(1));
	u2 : adder port map ( c(1) ,a(1),b(1),sum (1),c(2));
	u3 : adder port map ( c(2) ,a(2),b(2),sum (2),c(3));
	u4 : adder port map ( c(3) ,a(3),b(3),sum (3),c(4));
	u5 : adder port map ( c(4) ,a(4),b(4),sum (4),c(5));
	u6 : adder port map ( c(5) ,a(5),b(5),sum (5),c(6));
	u7 : adder port map ( c(6) ,a(6),b(6),sum (6),c(7));
	u8 : adder port map ( c(7) ,a(7),b(7),sum (7),co);
	
  -- <<enter your statements here>>
end addr_8_arch;