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library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity show is
port (
CLK: in STD_LOGIC;
D1: out STD_LOGIC_VECTOR (7 downto 0);
D2: out STD_LOGIC_VECTOR (7 downto 0)
);
end show;
architecture show_arch of prj_16 is
signal slow, cp: STD_LOGIC;
signal cp_cnt: STD_LOGIC_VECTOR (4 downto 0);
signal block_cnt: STD_LOGIC_VECTOR(2 downto 0);
signal cnt: STD_LOGIC_VECTOR(3 downto 0);
begin
process (CLK, slow) -- speed control
begin
if (CLK'event and CLK='1') then
cp_cnt<=cp_cnt+1;
if (slow='1') then
if (cp_cnt="11111") then
cp<='1';
else
cp<='0';
end if;
elsif (slow='0') then
if (cp_cnt(0)='1') then
cp<='1';
else
cp<='0';
end if;
end if;
end if;
end process;
process (cp)
begin
if (cp'event and cp='1') then
block_cnt<=block_cnt+1;
if (block_cnt="111") then
if (cnt="1111") then
slow<=not slow;
end if;
cnt<=cnt+1;
end if;
end if;
end process;
with block_cnt select
D2<="10000000" when "000",
"01000000" when "001",
"00100000" when "010",
"00010000" when "011",
"00001000" when "100",
"00000100" when "101",
"00000010" when "110",
"00000001" when "111",
"00000000" when others;
with cnt select
D1<="01111110" when "0000",
"00110000" when "0001",
"01101101" when "0010",
"01111001" when "0011",
"00110011" when "0100",
"01011011" when "0101",
"01011111" when "0110",
"01110000" when "0111",
"01111111" when "1000",
"01111011" when "1001",
"01110111" when "1010",
"00011111" when "1011",
"01001110" when "1100",
"00111101" when "1101",
"01001111" when "1110",
"01000111" when "1111",
"00000000" when others;
end show;
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