本人初学VHDL时编的比较系统的VHDL源程序 巨实用

library IEEE;
use IEEE.std_logic_1164.all;

package an3inv is
     component an3
          port (
                a1: in bit;
                a2: in bit;
                a3: in bit;
                o1: out bit
                );
  end component;
    component inv1
         port(a:in bit;
              b: out bit);
  end component;
end an3inv;
entity an3 is
       port( 
             a1: in bit;
             a2: in bit;
             a3: in bit;
             o1: out bit );                 
end an3;
architecture behavioral of an3 is
 begin
      o1<=a1 and a2 and a3;
end behavioral;
entity inv1 is
       port(a:in bit;
            b:out bit);
end inv1;
architecture behavioral of inv1 is
 begin 
      b<=not(a);
end behavioral;
use work.an3inv.all;
entity decode is
       port(a,b,en:in bit;
            q0,q1,q2,q3:out bit);
end decode;
architecture structural of decode is
    signal nota,notb:bit;
  begin
        i1:inv1 port map(a,nota);
        i2:inv1 port map(b,notb);
        A1:an3 port map(nota,en,notb,q0);         
        A2:an3 port map(a,en,notb,q1);
        A3:an3 port map(nota,en,b,q2);
        A4:an3 port map(a,en,b,q3);
end structural;