rom.vhd

来自「本人初学VHDL时编的比较系统的VHDL源程序 巨实用」· VHDL 代码 · 共 56 行

library  ieee;
use ieee.std_logic_1164.all;
package roms is 
	constant rom_width: integer:= 8 ;
	subtype rom_word is std_logic_vector ( rom_width-1 downto 0 );
	subtype rom_range is integer range 0 to 31;
	type rom_table is array ( 0 to 31) of rom_word;
	constant rom:rom_table := rom_table '(
	("10101000"),("11100000"),( "00000000"),( "01110101"),
	( "00000000"),( "00000000"),( "00000000"),( "00000000"),
	( "00000000"),( "00000000"),( "00000000"),( "00000000"),
	( "00000000"),( "00000000"),( "00000000"),( "00000000"),
	( "00000000"),( "00000000"),( "00000000"),( "00000000"),
	( "00000000"),( "00000000"),( "00000000"),( "00000000"),
	( "00000000"),( "00000000"),( "00000000"),( "00000000"),
	( "00000000"),( "00000000"),( "00000000"),( "00000000")
	);
	end roms;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;

use work.roms.all;

entity rom_32 is

port ( addr: in std_logic_vector ( 4 downto 0 );
clk:in std_logic;
rd: in std_logic;
data: out std_logic_vector ( 7 downto 0 ));
end rom_32 ;


architecture behavior of rom_32 is
begin 
output:process
        begin
          wait until clk'event and clk = '1';
	   if rd='1' then
	      data<= rom( conv_integer(addr)) ;
	   elsif rd = '0' then
	      data<= ( others=>'Z' );
	   end if ;
       end process output ;
end behavior;