本人初学VHDL时编的比较系统的VHDL源程序 巨实用

library IEEE;
use IEEE.std_logic_1164.all;

entity shift8 is
    port (
        a: in STD_LOGIC;
        clk: in STD_LOGIC;
        b: out STD_LOGIC
    );
end shift8;

architecture shift8_arch of shift8 is
component dff
	port ( d ,clk : in std_logic;
	q:out std_logic );
	end component ;
signal z: std_logic_vector ( 0 to 8 );

begin
z(0) <= a ;
g1: for i in 0 to 7 generate 
	dffx:dff port map ( z(i),clk ,z(i+1));
  	end generate;
  	b<= z(8);
  	  	-- <<enter your statements here>>
end shift8_arch;