本人初学VHDL时编的比较系统的VHDL源程序 巨实用

library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity dsf is
    port (
        a: in STD_LOGIC_VECTOR (6 downto 0);
        c: out STD_LOGIC
    );
end dsf;

architecture dsf_arch of dsf is
	signal tmp1: integer ;
	
begin
process ( a )
variable tmp: integer ;	
begin
	  	tmp := 0;
	  	for i in 0 to 6 loop
  			if a(i) ='1' then tmp := tmp +1 ; 
  			end if;
  		end loop;
       tmp1<=tmp;
end process ;
 with tmp1 select
        c<='1' when 4,
           '1' when 5,
           '1' when 6,
           '1' when 7,
           '0' when others;	 

  -- <<enter your statements here>>
end dsf_arch;