addr.vhd

本人初学VHDL时编的比较系统的VHDL源程序 巨实用

library IEEE;
use IEEE.std_logic_1164.all;

entity addr is
    port (
        a: in STD_LOGIC;
        b: in STD_LOGIC;
        ci: in STD_LOGIC;
        sum: out STD_LOGIC;
        co: out STD_LOGIC
    );
end addr;

architecture addr_arch of addr is
begin
 sum<= a xor b xor ci ;
 co <= (( a or b) and ci) or ( a and b);
  -- <<enter your statements here>>
end addr_arch;