本人初学VHDL时编的比较系统的VHDL源程序 巨实用

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity bmq is
    port (
        a: in STD_LOGIC_VECTOR (7 downto 0);
        b: out STD_LOGIC_VECTOR (7 downto 0)
    );
end bmq;

architecture bmq_arch of bmq is
begin
  b <= ( not a + '1'); -- <<enter your statements here>>
end bmq_arch;