10110101

本人初学VHDL时编的比较系统的VHDL源程序 巨实用

library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity count8 is
    port (
    	r: in std_logic;
        clk: in STD_LOGIC;
        cout: out std_logic
    );
end count8;

architecture count8_arch of count8 is

signal dd: std_logic_vector ( 2 downto 0 );

begin
	count: process ( r,clk  )
	begin
	if ( r='1' ) then dd<="000";
		elsif( clk'event and clk = '1') then
			dd <= dd + '1';
			end if ;
	
end process count ;
 with dd select
  cout<='1'when"000",
     	'0'when"001",
     	'1'when"010",
     	'1'when"011",
     	'0'when"100",
     	'1'when"101",
     	'0'when"110",
     	'1'when"111",
     	'0'when others ;
     			
end count8_arch;