本人初学VHDL时编的比较系统的VHDL源程序 巨实用

library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity count8 is
    port (
    	r: in std_logic;
        clk: in STD_LOGIC;
        cout: out STD_LOGIC_VECTOR (7 downto 0)
    );
end count8;

architecture count8_arch of count8 is

signal dd: std_logic_vector ( 2 downto 0 );

begin
	count: process (r, clk  )
	begin
	if ( r='1' ) then dd<="000";
	elsif( clk'event and clk = '1') then
			dd <= dd + '1';
			end if ;
	
end process count ;
 with dd select
  cout<="00000001"when"000",
     	"00000010"when"001",
     	"00000100"when"010",
     	"00001000"when"011",
     	"00010000"when"100",
     	"00100000"when"101",
     	"01000000"when"110",
     	"10000000"when"111",
     	"00000000"when others ;
     			
end count8_arch;