本人初学VHDL时编的比较系统的VHDL源程序 巨实用

library ieee;

use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity cnt8 is port(
	clk,rst: in std_logic;
	en,load: in std_logic;
	upper_enable : in std_logic;
	lower_enable : in std_logic;
	data: in std_logic_vector( 7 downto 0 );
	cnt: buffer std_logic_vector ( 7 downto 0));
	end cnt8;
	
architecture archcnt8 of cnt8 is

signal d: std_logic_vector ( 7 downto 0);

begin
	count : process ( rst,clk)
	begin if rst='1' then 
			d <= ( others => '0');
		elsif ( clk'event and clk='1')then
			if load = '1' then
				d <= data ;
				elsif en = '1' then
					d <= d-'1';
				end if;
			end if; 
	end process count ;

	a:process (upper_enable ,lower_enable)
	begin
	if (upper_enable='0' ) and ( lower_enable='1' ) then
	      cnt(3 downto 0)<=d(3 downto 0);
	      cnt(7 downto 4)<="ZZZZ";
	elsif (upper_enable='1' ) and ( lower_enable='0' )then
	      cnt(7 downto 4)<=d(7 downto 4);
	      cnt(3 downto 0)<="ZZZZ";
	elsif (upper_enable='1' ) and ( lower_enable='1' )then
	            cnt <= d;
	else 
	         cnt<="ZZZZZZZZ";
	end if;
	end process a;

end archcnt8;