programcounter.v.bak

用verilog编写在FLEX10K上实现的简易CPU

//PC
//the control signal is considered to coordinate the addr_in and add_jmp

module programcounter(addr_in, rst, clk, pc_en, add_jmp, addr_out);
	input  addr_in, rst, clk, add_jmp, pc_en;
	output  addr_out;
	
	wire[15:0]  addr_in, addr_out;
	reg[15:0] pc;
	
	assign addr_out = pc;
	
	always@(posedge clk)
	begin
		if(rst)
			pc <= 16'h0000;
		else
			if(pc_en)
				if(!add_jmp)
					pc <= pc + 1;
				else
					pc <= addr_in;
			else
				pc <= pc;
	end
	
endmodule