pciscc_drv.h

高速同步串口芯片PEB20534的驱动程序

#define  XMR			0x00002000	/* Transmit Message Repeat */
#define  XON			0x00002000	/* XOFF Character Detected Interrupt */
#define  CSC			0x00004000	/* /CTS Status Change */
#define  TIN			0x00008000	/* Timer Interrupt */
#define  XDU			0x00010000	/* Transmit Data Underrun Interrupt */
#define  ALLS			0x00040000	/* All Sent Interrupt */

/* Peripheral control registers */
#define LCONF			0x0300		/* LBI Configuration Register */
#define  MCTC			0x00000001	/* LBI Memory Cycle Time Control */
#define  ABM			0x00000010	/* LBI Arbitration Master */
#define  RDEN			0x00000020	/* LBI LRDY Enable */
#define  BTYP			0x00000040	/* LBI Bus Type */
#define  BTYP0			0x00000040
#define  BTYP1			0x00000080
#define  HDEN			0x00000100	/* LBI HOLD Enable */
#define  EALE			0x00000200	/* LBI Extended ALE */
#define  EBCRES			0x00400000	/* LBI External Bus Controller Reset */
#define  LINTIC			0x80000000	/* LBI Interrupt Input Control */
#define SSCCON			0x0380		/* SSC Control Register */
#define  SSCBM			0x00000001	/* SSC Data Width Control */
#define  SSCBC			0x00000001	/* SSC Shift Counter */
#define  SSCHB			0x00000010	/* SSC Heading (Bit Order) Control */
#define  SSCPH			0x00000020	/* SSC Clock Phase Control */
#define  SSCPO			0x00000040	/* SSC Polarity Control */
#define  SSCTEN			0x00000100	/* SSC Transmit Error Enable */
#define  SSCTE			0x00000100	/* SSC Transmit Status Flag */
#define  SSCREN			0x00000200	/* SSC Receive Error Enable */
#define  SSCRE			0x00000200	/* SSC Receive Status Flag */
#define  SSCPEN			0x00000400	/* SSC Phase Error Enable */
#define  SSCPE			0x00000400	/* SSC Baud Rate Status Flag */
#define  SSCBEN			0x00000800	/* SSC Baud Rate Error Enable */
#define  SSCBE			0x00000800	/* SSC Baud Rate Status Flag */
#define  SSCBSY			0x00001000	/* SSC Busy Flag */
#define  SSCMS			0x00004000	/* SSC Master Select */
#define  SSCEN			0x00008000	/* SSC Enable */
#define SSCBR			0x0384		/* SSC Baud Rate Generator Register */
#define SSCTB			0x0388		/* SSC Transmit Buffer */
#define SSCRB			0x038c		/* SSC Receive Buffer */
#define SSCCSE			0x0390		/* SSC Chip Select Enable Register */
#define  ASEL0			0x00000010	/* SSC Chipselect 0 */
#define  ASEL1			0x00000020	/* SSC Chipselect 1 */
#define  ASEL2			0x00000040	/* SSC Chipselect 2 */
#define  ASEL3			0x00000080	/* SSC Chipselect 3 */
#define SSCIM			0x0394		/* SSC Interrupt Mask Register */
#define  IMTX			0x00000001	/* SSC Transmit Interrupt Mask */
#define  IMER			0x00000002	/* SSC Error Interrupt Mask */
#define  IMRX			0x00000004	/* SSC Receive Interrupt Mask */
#define GPDIR			0x0400		/* GPP Direction Configuration Register */
#define GPDATA			0x0404		/* GPP Data I/O Register */
#define GPIM			0x0408		/* GPP Interrupt Mask Register */

/* Receive Data Section Status Byte (HDLC mode) */
#define SB_LA			0x00000001	/* low byte address compare */
#define SB_CR			0x00000002	/* command/response */
#define SB_HA0			0x00000004	/* high byte address compare */
#define SB_HA1			0x00000008
#define SB_RAB			0x00000010	/* receive message aborted */
#define SB_CRC			0x00000020	/* CRC compare */
#define SB_RDO			0x00000040	/* receive data overflow */
#define SB_VFR			0x00000080	/* valid frame */

/* Configuration Interrupt Vector */
#define CIV_ARACK		0x00000001	/* action request acknowledge */
#define CIV_ARF			0x00000002	/* action request failed */
#define	CIV_SRCID		0x10000000	/* source ID, always 0x0a */
#define CIV_SRCIDVAL	0x0a

/* DMA Controller Interrupt Vector */
#define DMACIV_ERR		0x00010000	/* error indication interrupt */
#define DMACIV_FI		0x00020000	/* frame indication interrupt */
#define DMACIV_HI		0x00040000	/* host initiated interrupt */
#define DMACIV_SRCID	0x10000000

/* SCC Interrupt Vector */
#define SCCIV_FLEX		0x00000001	/* Frame Length Exceeded Interrupt */
#define SCCIV_RFO		0x00000002	/* RX FIFO Overflow Interrupt */
#define SCCIV_CDSC		0x00000004	/* Carrier Detect Status Change Interrupt */
#define SCCIV_PLLA		0x00000008	/* DPLL Asynchronous Interrupt */
#define SCCIV_PCE		0x00000010	/* Protocol Error Interrupt */
#define SCCIV_FERR		0x00000010	/* Framing Error Interrupt */
#define SCCIV_SCD		0x00000010	/* SYN Character Detected Interrupt */
#define SCCIV_RSC		0x00000020	/* Receive Status Change Interrupt */
#define SCCIV_PERR		0x00000020	/* Parity Error Interrupt */
#define SCCIV_RFS		0x00000040	/* Receive Frame Start Interrupt */
#define SCCIV_TIME		0x00000040	/* Time Out Interrupt */
#define SCCIV_RDO		0x00000080	/* Receive Data Overflow Interrupt */
#define SCCIV_TCD		0x00000080	/* Termination Character Detected Interrupt */
#define SCCIV_BRKT		0x00000100	/* Break Terminated Interrupt */
#define SCCIV_BRK		0x00000200	/* Break Interrupt */
#define SCCIV_XPR		0x00001000	/* Transmit Pool Ready Interrupt */
#define SCCIV_XMR		0x00002000	/* Transmit Message Repeat */
#define SCCIV_XOFF		0x00002000	/* XOFF Character Detected Interrupt */
#define SCCIV_CSC		0x00004000	/* /CTS Status Change */
#define SCCIV_TIN		0x00008000	/* Timer Interrupt */
#define SCCIV_XDU		0x00010000	/* Transmit Data Underrun Interrupt */
#define SCCIV_ALLS		0x00040000	/* All Sent Interrupt */
#define SCCIV_SRCID		0x10000000
#define SCCIV_SCC		0x02000000	/* 1: SCC generated. 0: DMAC generated */
#define SCCIV_ERR		0x00010000	/* ERROR Indication Interrupt */
#define SCCIV_FI		0x00020000	/* Frame Indication Interrupt */
#define SCCIV_HI		0x00040000	/* Host Initiated Interrupt */
#define SCCIV_IGNORE	0x00100000	/* internal use */

/* SSC Interrupt Vector */
#define SSCIV_INSW		0x00000001	/* interrupt status word */
#define SSCIV_TX		0x00010000	/* transmit interrupt */
#define SSCIV_RX		0x00020000	/* receive interrupt */
#define SSCIV_ERR		0x00040000	/* error interrupt */
#define SSCIV_DE		0x00800000	/* data/error indication */
#define SSCIV_RT		0x01000000	/* rx/tx indicator */
#define SSCIV_SRCID		0x10000000
#define SSCIV_SRCIDVAL	0x0c

/* LBI Interrupt Vector */
#define LBIIV_SRCID		0x10000000
#define LBIIV_SRCIDVAL	0x0d

/* GPP Interrupt Vector */
#define GPPIV_GPDATA	0x00000001
#define GPPIV_SRCID		0x10000000
#define GPPIV_SRCIDVAL	0x0f

/* TX state definition */
#define	TX_RESET		0
#define TX_IDLE			1
#define	TX_DELAY		2
#define	TX_XMIT			3
#define TX_TAIL			4
#define TX_CAL			5
#define	TX_STALL		6

/* TX descriptor */
struct tx_desc {
	ULONG			flags;
#define NO		0x00010000			/* number of bytes */
#define HI		0x20000000			/* host initiated interrupt */
#define HOLD	0x40000000			/* last descriptor in chain */
#define FE		0x80000000			/* frame end */
	ULONG			nextptr;
	ULONG			dataptr;
	ULONG			result;
#define C			0x40000000		/* descriptor complete flag */
	L1FRAME			*l1_frame;		/* pointer to frame buffer */
	struct tx_desc	*next;			/* note virtaddr */
	struct tx_desc	*prev;
};

/* RX descriptor */
struct rx_desc {
	ULONG			flags;
#define RA		0x00000200			/* receive abort */
	ULONG			nextptr;		/* note busaddr */
	ULONG			dataptr;
	ULONG			result;
	ULONG			feptr;
	L1FRAME			*l1_frame;		/* pointer to frame buffer */
	struct rx_desc	*next;			/* note virtaddr */
	struct rx_desc	*prev;			/* previous */
};

/* chip communication buffers */
typedef struct {
	ULONG			iq_per[CFG_IQLEN];		/* IQ_PER/IQ_CFG buffer */
	ULONG			iq_cfg[CFG_IQLEN];
	ULONG			iq_rx[4][CFG_IQLEN];	/* IQ_RX/IQ_TX buffer */
	ULONG			iq_tx[4][CFG_IQLEN];
	struct rx_desc	dq_rx[4][CFG_RX_DESC];	/* RX/TX descriptors */
	struct tx_desc	dq_tx[4][CFG_TX_DESC];
	PCHAR			dummy[256];				/* dummy buffer */
} DMA_BUFFERS, *PDMA_BUFFERS;

/* channel data/state */
typedef struct {
	L1_STATISTICS	stats;			/* statistics */
	ULONG			initialized;	/* channel initialized? */
	PULONG			iq_rx;			/* interrupt queues */
	PULONG			iq_tx;
	PULONG			iq_rx_next;		/* next entry to be processed */
	PULONG			iq_tx_next;
	struct rx_desc	*dq_rx;			/* RX descriptor queue */
	struct rx_desc	*dq_rx_next;
	struct tx_desc	*dq_tx;			/* TX descriptor queue */
	struct tx_desc	*dq_tx_last;
	struct tx_desc	*dq_tx_cleanup;
	ULONG			tx_enqueued;	/* number of enqueued TX frames */
	ULONG			bitrate;		/* effective bitrate */
	ULONG			mode;			/* mode flags */
	volatile ULONG	txstate;
	volatile ULONG	rx_mailbox;		/* communication with isr */
	volatile ULONG	tx_mailbox;		/* communication with isr */
	ULONG			ccr0;			/* SCC register contents */
	ULONG			ccr1;
	ULONG			ccr2;
} CHANNEL_INFO, *PCHANNEL_INFO;

/* driver local data structure */
typedef struct {
    PHYSICAL_ADDRESS	Address;		/* base address */
	ULONG				AddrLen;		/* address space length */
    PVOID				MappedAddress;	/* mapped base address */
	KIRQL				IrqLevel;		/* IRQ level */
	ULONG				IrqVector;		/* IRQ vector */
	KAFFINITY			IrqAffinity;	/* IRQ affinity */
	PKINTERRUPT			IrqObject;		/* IRQ object */
	KSPIN_LOCK			Lock;			/* shared access lock */
	KDPC				TxResetDpc;		/* TX underrun reset DPC */
	KDPC				IsrDpc;			/* TX/RX ISR bottom half */
	PULONG				iq_per;			/* peripheral interrupt queue */
	PULONG				iq_cfg;			/* configuration interrupt queue */
	PULONG				iq_per_next;	/* next entry to be processed */
	PULONG				iq_cfg_next;
	ULONG				initialized;	/* chip initialized? */
	volatile ULONG		mailbox;		/* communication with isr */
#define MAILBOX_NONE	0
#define MAILBOX_OK		1
#define MAILBOX_FAILURE	2
	ULONG				OpenCnt;		/* open driver handles */
	ULONG				ReadMode;		/* blocking/non-blocking read */
	LIST_ENTRY			RxQueue;		/* receiver frame list */
	LIST_ENTRY			RxPending;		/* Pending IRP list */
	CHANNEL_INFO		Channel[4];		/* channel specific data */
	PDMA_BUFFERS		DmaBuffers;		/* chip communication buffers */
} LOCAL_DEVICE_INFO, *PLOCAL_DEVICE_INFO;

/* xmit synchronization call structure */
typedef struct {
	PLOCAL_DEVICE_INFO	pLDI;
	L1FRAME				*tx_frame;
} XMIT_SYNC_INFO, *PXMIT_SYNC_INFO;

/* calib synchronization call structure */
typedef struct {
	PLOCAL_DEVICE_INFO	pLDI;
	ULONG				chan;
	ULONG				time;
} CALIB_SYNC_INFO, *PCALIB_SYNC_INFO;

/* function prototypes */
NTSTATUS	DriverEntry(			IN  PDRIVER_OBJECT DriverObject,
									IN  PUNICODE_STRING RegistryPath);

NTSTATUS	pciscc_create(			IN	PDEVICE_OBJECT pDO,
									IN	PIRP pIrp);

NTSTATUS	pciscc_close(			IN	PDEVICE_OBJECT pDO,
									IN	PIRP pIrp);

NTSTATUS	pciscc_read(			IN	PDEVICE_OBJECT pDO,
									IN	PIRP pIrp);

NTSTATUS	pciscc_write(			IN	PDEVICE_OBJECT pDO,
									IN	PIRP pIrp);

NTSTATUS	pciscc_ioctl(			IN	PDEVICE_OBJECT pDO,
									IN	PIRP pIrp);

VOID		pciscc_unload(			IN	PDRIVER_OBJECT DriverObject);

VOID		pciscc_cancel(			IN	PDEVICE_OBJECT pDO,
									IN	PIRP pIrp);

VOID		pciscc_clear_rxlist(	IN	PLOCAL_DEVICE_INFO pLDI);

VOID		pciscc_clear_rxpending(	IN	PLOCAL_DEVICE_INFO pLDI);

VOID		pciscc_free_resources(	IN	PDRIVER_OBJECT DriverObject);

PVOID		pciscc_alloc(			IN	ULONG uSize);

VOID		pciscc_free(			IN	PVOID BaseAddr);

ULONG		ReadL(					IN	PLOCAL_DEVICE_INFO pLDI, 
									IN	ULONG Offset);

VOID		WriteL(					IN	PLOCAL_DEVICE_INFO pLDI, 
									IN	ULONG Offset,
									IN	ULONG Value);

ULONG		VirtToPhys(				IN	PVOID Address);

NTSTATUS	pciscc_nt_config(		IN	PDRIVER_OBJECT  DriverObject,
									IN	PUNICODE_STRING RegistryPath,
									IN	PLOCAL_DEVICE_INFO pLDI);

NTSTATUS	pciscc_init_queues(		IN	PLOCAL_DEVICE_INFO pLDI,
									IN	ULONG chan);

NTSTATUS	pciscc_chip_open(		IN	PLOCAL_DEVICE_INFO pLDI);

VOID		pciscc_chip_close(		IN	PLOCAL_DEVICE_INFO pLDI);

NTSTATUS	pciscc_channel_open(	IN	PLOCAL_DEVICE_INFO pLDI,
									IN	ULONG chan,
									IN	ULONG bitrate,
									IN	ULONG mode);

VOID		pciscc_channel_close(	IN	PLOCAL_DEVICE_INFO pLDI,
									IN	ULONG chan);

VOID		pciscc_set_baud(		IN	PLOCAL_DEVICE_INFO pLDI,
									IN	ULONG chan,
									IN	ULONG rate);

ULONG		pciscc_state(			IN	PLOCAL_DEVICE_INFO pLDI,
									IN	ULONG chan);

BOOLEAN		pciscc_calib_sync(		IN	PCALIB_SYNC_INFO pInfo);

BOOLEAN		pciscc_xmit_sync(		IN	PXMIT_SYNC_INFO pInfo);

BOOLEAN		pciscc_isr(				IN	PKINTERRUPT Interrupt,
									IN	PVOID ServiceContext);

VOID		pciscc_dpc_txreset(		IN	PKDPC Dpc,
									IN	PDEVICE_OBJECT pDO,
									IN	PVOID SystemArgument1,
									IN	PVOID SystemArgument2);

VOID		pciscc_dpc_isr(			IN	PKDPC Dpc,
									IN	PDEVICE_OBJECT pDO,
									IN	PVOID SystemArgument1,
									IN	PVOID SystemArgument2);

#endif	/* _PCISCC_H_ */