pciscc_drv.h

高速同步串口芯片PEB20534的驱动程序

#ifndef _PCISCC_H_
#define _PCISCC_H_

#include <ntddk.h>
#include <devioctl.h>
#include "pciscc_flex.h"

/* File system device name.*/
#define PCISCC_W32_NAME L"\\DosDevices\\PCISCC"
#define PCISCC_NT_NAME	L"\\Device\\PCISCC0"

/* PEB-20534H PCI identification */
#define	PCI_VENDOR_ID	0x110A
#define	PCI_DEVICE_ID	0x2102

/* Chip parameters */
#define	CFG_IQLEN		32		/* Interrupt queue length */
#define	CFG_TX_DESC		16		/* TX descriptors */
#define	CFG_RX_DESC		16		/* RX descriptors */
#define	CFG_FIFO_RX_T	64		/* RX FIFO DMA init threshold dwords */

#define	CFG_MTU			384		/* maximum transfer unit */

/* General Registers */
#define GCMDR			0x0000		/* Global Command Register */
#define  AR				0x00000001	/* Action Request */
#define  IMAR			0x00000200	/* Interrupt Mask Action Request */
#define  TXPR0			0x00000400	/* Transmit Poll Request Channel 0 */
#define  TXPR1			0x00000800	/* Transmit Poll Request Channel 1 */
#define  TXPR2			0x00001000	/* Transmit Poll Request Channel 2 */
#define  TXPR3			0x00002000	/* Transmit Poll Request Channel 3 */
#define  CFGIQP			0x00100000	/* Configure IQ Peripheral */
#define  CFGIQCFG		0x00200000	/* Configure IQ Peripheral */
#define  CFGIQSCC0TX	0x01000000	/* Configure IQ SCC0 Transmit */
#define  CFGIQSCC1TX	0x02000000	/* Configure IQ SCC1 Transmit */
#define  CFGIQSCC2TX	0x04000000	/* Configure IQ SCC2 Transmit */
#define  CFGIQSCC3TX	0x08000000	/* Configure IQ SCC3 Transmit */
#define  CFGIQSCC0RX	0x10000000	/* Configure IQ SCC0 Receive */
#define  CFGIQSCC1RX	0x20000000	/* Configure IQ SCC1 Receive */
#define  CFGIQSCC2RX	0x40000000	/* Configure IQ SCC2 Receive */
#define  CFGIQSCC3RX	0x80000000	/* Configure IQ SCC3 Receive */
#define GSTAR			0x0004		/* Global Status Register */
#define  ARACK			0x00000001	/* Action Request Acknowledge Status */
#define  ARF			0x00000002	/* Action Request Failed Status */
#define  IIPGPP			0x00010000	/* Int. Indication Peripheral Queue GPP */
#define  IIPLBI			0x00040000	/* Int. Indication Peripheral Queue LBI */
#define  IIPSSC			0x00080000	/* Int. Indication Peripheral Queue SSC */
#define  IICFG			0x00200000	/* Int. Indication Configuration Queue */
#define  IISCC0TX		0x01000000	/* Int. Indication Queue SCC0 TX */
#define  IISCC1TX		0x02000000	/* Int. Indication Queue SCC1 TX */
#define  IISCC2TX		0x04000000	/* Int. Indication Queue SCC2 TX */
#define  IISCC3TX		0x08000000	/* Int. Indication Queue SCC3 TX */
#define  IISCC0RX		0x10000000	/* Int. Indication Queue SCC0 RX */
#define  IISCC1RX		0x20000000	/* Int. Indication Queue SCC1 RX */
#define  IISCC2RX		0x40000000	/* Int. Indication Queue SCC2 RX */
#define  IISCC3RX		0x80000000	/* Int. Indication Queue SCC3 RX */
#define GMODE			0x0008		/* Global Mode Register */
#define  CMODE			0x00000001	/* DMA Control Mode */
#define  DBE			0x00000002	/* DEMUX Burst Enable */
#define  ENDIAN			0x00000004	/* Endian Selection */
#define  CHN			0x00002000	/* Channel Number Highest Priority */
#define  SPRI			0x00008000	/* Select Priority */
#define  PERCFG			0x00010000	/* Peripheral Block Configuration */
#define  LCD			0x00080000	/* LBI Clock Division */
#define  OSCPD			0x00200000	/* Oscillator Power Down */

/* IRQ Queue Control Registers */
#define IQLENR1		0x000c		/* Interrupt Queue Length Register 1 */
#define  IQSCC0TXLEN	0x00001000	/* Interrupt Queue SCC0 TX Length */
#define  IQSCC1TXLEN	0x00000100	/* Interrupt Queue SCC1 TX Length */
#define  IQSCC2TXLEN	0x00000010	/* Interrupt Queue SCC2 TX Length */
#define  IQSCC3TXLEN	0x00000001	/* Interrupt Queue SCC3 TX Length */
#define  IQSCC0RXLEN	0x10000000	/* Interrupt Queue SCC0 RX Length */
#define  IQSCC1RXLEN	0x01000000	/* Interrupt Queue SCC1 RX Length */
#define  IQSCC2RXLEN	0x00100000	/* Interrupt Queue SCC2 RX Length */
#define  IQSCC3RXLEN	0x00010000	/* Interrupt Queue SCC3 RX Length */
#define IQLENR2			0x0010		/* Interrupt Queue Length Register 2 */
#define  IQPLEN			0x00010000	/* Interrupt Queue Peripheral Length */
#define  IQCFGLEN		0x00100000	/* Interrupt Queue Configuration Length */
#define IQSCC0RXBAR		0x0014		/* Interrupt Queue SCC0 RX Base Address */
#define IQSCC1RXBAR		0x0018		/* Interrupt Queue SCC1 RX Base Address */
#define IQSCC2RXBAR		0x001c		/* Interrupt Queue SCC2 RX Base Address */
#define IQSCC3RXBAR		0x0020		/* Interrupt Queue SCC3 RX Base Address */
#define IQSCC0TXBAR		0x0024		/* Interrupt Queue SCC0 TX Base Address */
#define IQSCC1TXBAR		0x0028		/* Interrupt Queue SCC1 TX Base Address */
#define IQSCC2TXBAR		0x002c		/* Interrupt Queue SCC2 TX Base Address */
#define IQSCC3TXBAR		0x0030		/* Interrupt Queue SCC3 TX Base Address */
#define FIFOCR4			0x0034		/* FIFO Control Register 4 */
#define  TFFTHRES0		0x00000001	/* Transmit FIFO Forward Threshold Chan. 0 */
#define  TFFTHRES1		0x00000100	/* Transmit FIFO Forward Threshold Chan. 1 */
#define  TFFTHRES2		0x00010000	/* Transmit FIFO Forward Threshold Chan. 2 */
#define  TFFTHRES3		0x01000000	/* Transmit FIFO Forward Threshold Chan. 3 */
#define IQCFGBAR		0x003c		/* CFG Interrupt Queue Base Address */
#define IQPBAR			0x0040		/* PER Interrupt Queue Base Address */

/* DMAC control registers */
#define FIFOCR1			0x0044		/* FIFO Control Register 1 */
#define  TFSIZE0		0x08000000	/* Transmit FIFO Size Channel 0 */
#define  TFSIZE1		0x00400000	/* Transmit FIFO Size Channel 1 */
#define  TFSIZE2		0x00020000	/* Transmit FIFO Size Channel 2 */
#define  TFSIZE3		0x00000800	/* Transmit FIFO Size Channel 3 */
#define FIFOCR2			0x0048		/* FIFO Control Register 2 */
#define  M4_0			0x00000080	/* Multiplier 4 FIFO Channel 0 */
#define  M2_0			0x00000040	/* Multiplier 2 FIFO Channel 0 */
#define  M4_1			0x00000020	/* Multiplier 4 FIFO Channel 1 */
#define  M2_1			0x00000010	/* Multiplier 2 FIFO Channel 1 */
#define  M4_2			0x00000008	/* Multiplier 4 FIFO Channel 2 */
#define  M2_2			0x00000004	/* Multiplier 2 FIFO Channel 2 */
#define  M4_3			0x00000002	/* Multiplier 4 FIFO Channel 3 */
#define  M2_3			0x00000001	/* Multiplier 2 FIFO Channel 3 */
#define  TFRTHRES0		0x08000000	/* Transmit FIFO Refill Threshold Chan. 0 */
#define  TFRTHRES1		0x00400000	/* Transmit FIFO Refill Threshold Chan. 1 */
#define  TFRTHRES2		0x00020000	/* Transmit FIFO Refill Threshold Chan. 2 */
#define  TFRTHRES3		0x00000800	/* Transmit FIFO Refill Threshold Chan. 3 */
#define FIFOCR3			0x004c		/* FIFO Control Register 3 */
#define  RFTHRES		0x00000001	/* RX FIFO Threshold */
#define  M2				0x00000080	/* RX FIFO Threshold Multiplier 2 */
#define  M4				0x00000100	/* RX FIFO Threshold Multiplier 4 */
#define CH0CFG			0x0050		/* Channel 0 Configuration */
#define CH0BRDA			0x0054		/* Channel 0 Base Address RX Descriptor */
#define CH0BTDA			0x0058		/* Channel 0 Base Address TX Descriptor */
#define CH1CFG			0x005c		/* Channel 1 Configuration */
#define CH1BRDA			0x0060		/* Channel 1 Base Address RX Descriptor */
#define CH1BTDA			0x0064		/* Channel 1 Base Address TX Descriptor */
#define CH2CFG			0x0068		/* Channel 2 Configuration */
#define CH2BRDA			0x006c		/* Channel 2 Base Address RX Descriptor */
#define CH2BTDA			0x0070		/* Channel 2 Base Address TX Descriptor */
#define CH3CFG			0x0074		/* Channel 3 Configuration */
#define CH3BRDA			0x0078		/* Channel 3 Base Address RX Descriptor */
#define CH3BTDA			0x007c		/* Channel 3 Base Address TX Descriptor */
#define  IDT			0x00080000
#define  IDR			0x00100000
#define  RDT			0x00200000
#define  RDR			0x00400000
#define  MTERR			0x01000000	/* Mask TX ERR-Interrupt */
#define  MRERR			0x02000000	/* Mask RX ERR-Interrupt */
#define  MTFI			0x04000000	/* Mask RX FI-Interrupt */
#define  MRFI			0x08000000	/* Mask TX FI-Interrupt */
#define CH0FRDA			0x0098		/* Channel 0 First RX Descriptor Address */
#define CH1FRDA			0x009c		/* Channel 1 First RX Descriptor Address */
#define CH2FRDA			0x00a0		/* Channel 2 First RX Descriptor Address */
#define CH3FRDA			0x00a4		/* Channel 3 First RX Descriptor Address */
#define CH0FTDA			0x00b0		/* Channel 0 First TX Descriptor Address */
#define CH1FTDA			0x00b4		/* Channel 1 First TX Descriptor Address */
#define CH2FTDA			0x00b8		/* Channel 2 First TX Descriptor Address */
#define CH3FTDA			0x00bc		/* Channel 3 First TX Descriptor Address */
#define CH0LRDA			0x00c8		/* Channel 0 Last RX Descriptor Address */
#define CH1LRDA			0x00cc		/* Channel 1 Last RX Descriptor Address */
#define CH2LRDA			0x00d0		/* Channel 2 Last RX Descriptor Address */
#define CH3LRDA			0x00d4		/* Channel 3 Last RX Descriptor Address */
#define CH0LTDA			0x00e0		/* Channel 0 Last TX Descriptor Address */
#define CH1LTDA			0x00e4		/* Channel 1 Last TX Descriptor Address */
#define CH2LTDA			0x00e8		/* Channel 2 Last TX Descriptor Address */
#define CH3LTDA			0x00ec		/* Channel 3 Last TX Descriptor Address */

/* SCC base addresses */
unsigned long SCCBASE[] = {0x0100, 0x0180, 0x0200, 0x0280};

/* SCC registers */
#define CMDR			0x0000		/* Command Register */
#define  RNR			0x00000001	/* Receiver Not Ready Command */
#define  STI			0x00000100	/* Start Timer Command */
#define  RRES			0x00010000	/* Receiver Reset Command */
#define  RFRD			0x00020000	/* Receive FIFO Read Enable Command */
#define  HUNT			0x00040000	/* Enter Hunt State Command */
#define  XRES			0x01000000	/* Transmitter Reset Command */
#define STAR			0x0004		/* Status Register */
#define  RRNR			0x00010000	/* Received RNR Status */
#define  XRNR			0x00020000	/* Transmit RNR Status */
#define  WFA			0x00040000	/* Wait For Acknowledgement */
#define  DPLA			0x00080000	/* DPLL Asynchronous */
#define  RLI			0x00100000	/* Receive Line Inactive */
#define  CD				0x00200000	/* Carrier Detect Input Signal State */
#define  RFNE			0x00400000	/* Receive FIFO Not Empty */
#define  SYNC			0x00800000	/* Synchronisation Status */
#define  CTS			0x01000000	/* Clear To Send Input Signal State */
#define  FCS			0x08000000	/* Flow Control Status */
#define  CEC			0x10000000	/* Command Executing */
#define  TEC			0x20000000	/* TIC executing */
#define CCR0			0x0008		/* Channel Configuration Register 0 */
#define  CM				0x00000001	/* Clock Mode */
#define  CM0			0x00000001
#define  CM1			0x00000002
#define  CM2			0x00000004
#define  HS				0x00000008	/* High Speed (PEB-20534H-52) */
#define  SSEL			0x00000010	/* Clock Source Select (a/b Select) */
#define  TOE			0x00000020	/* Transmit Clock Out Enable */
#define  BCR			0x00000080	/* Bit Clock Rate */
#define	 PSD			0x00000100	/* DPLL Phase Shift Disable */
#define  VIS			0x00001000	/* Masked Interrupts Visible */
#define  SM				0x00010000	/* Serial Port Mode */
#define  SM0			0x00010000
#define	 SM1			0x00020000
#define  SC				0x00100000	/* Serial Port Configuration */
#define  SC0			0x00100000
#define  SC1			0x00200000
#define  SC2			0x00400000
#define  PU				0x80000000	/* Power Up */
#define CCR1			0x000c		/* Channel Configuration Register 1 */
#define  C32			0x00000001	/* CRC-32 Select */
#define  TOLEN			0x00000001	/* Time Out Length */
#define  CRL			0x00000002	/* CRC Reset Value */
#define  SFLAG			0x00000080	/* Shared Flags Transmission */
#define  TOIE			0x00000080	/* Time Out Indication Enable */
#define  TLP			0x00000100	/* Test Loop */
#define  MCS			0x00000200	/* Modulo Count Select */
#define  PPM0			0x00000400	/* PPP Mode Select 0 */
#define  BISNC			0x00000400	/* Enable BISYNC Mode */
#define  PPM1			0x00000800	/* PPP Mode Select 1 */
#define  SLEN			0x00000800	/* SYNC Character Length */
#define  NRM			0x00001000	/* Normal Response Mode */
#define  ADM			0x00002000	/* Address Mode Select */
#define  MDS0			0x00004000	/* Mode Select (HDLC Protocol Sub-Mode) */
#define  MDS1			0x00008000
#define  CAS			0x00020000	/* Carrier Detect Auto Start */
#define  FCTS			0x00040000	/* Flow Control (Using Signal /CTS) */
#define  FRTS			0x00080000	/* Flow Control (Using Signal /RTS) */
#define  RTS			0x00100000	/* Request To Send Pin Control */
#define  TCLKO			0x00200000	/* Transmit Clock Output */
#define  ICD			0x00400000	/* Invert Carrier Detect Pin Polarity */
#define  ODS			0x02000000	/* Output Driver Select */
#define  DIV			0x04000000	/* Data Inversion */
#define  SOC0			0x10000000	/* Serial Output Control */
#define  SOC1			0x20000000
#define CCR2			0x0010		/* Channel Configuration Register 2 */
#define  XCRC			0x00000001	/* Transmit CRC Checking Mode */
#define  FLON			0x00000001	/* Flow Control Enable */
#define  CRCM			0x00000001	/* CRC Mode Select */
#define  OIN			0x00000002	/* One Insertion */
#define  CAPP			0x00000002	/* CRC Append */
#define  SXIF			0x00000004	/* Selects Transmission Of I-Frames */
#define  CRLBS			0x00000004	/* CRC Reset Value In BISYNC Mode */
#define  ITF			0x00000008	/* Interframe Time Fill */
#define  PRE0			0x00000010	/* Number Of Preamble Repetitions */
#define  PRE1			0x00000020
#define  EPT			0x00000080	/* Enable Preamble Transmission */
#define  PRE			0x00000100	/* Preamble */
#define  RFTH			0x00010000	/* Receive FIFO Threshold */
#define  RFDF			0x00080000	/* Receive FIFO Data Format */
#define  RADD			0x00100000	/* Receive Address Pushed To FIFO */
#define  DPS			0x00100000	/* Data Parity Storage */
#define  RCRC			0x00200000	/* Receive CRC Checking Mode */
#define  PARE			0x00200000	/* Parity Enable */
#define  DRCRC			0x00400000	/* Disable Receive CRC Checking */
#define  PAR0			0x00400000	/* Parity Format */
#define  PAR1			0x00800000
#define  STOP			0x01000000	/* Stop Bit Number */
#define  SLOAD			0x01000000	/* Enable SYNC Character Load */
#define  XBRK			0x02000000	/* Transmit Break */
#define  DXS			0x04000000	/* Disable Storage of XON/XOFF-Characters */
#define  RAC			0x08000000	/* Receiver Active */
#define  CHL0			0x10000000	/* Character Length */
#define  CHL1			0x20000000
#define ACCM			0x0014		/* ASYNC Control Character Map */
#define UDAC			0x0018		/* User Defined ASYNC Character */
#define  AC0			0x00000001	/* User Defined ASYNC Character Control Map */
#define  AC1			0x00000100	/* User Defined ASYNC Character Control Map */
#define  AC2			0x00010000	/* User Defined ASYNC Character Control Map */
#define  AC3			0x01000000	/* User Defined ASYNC Character Control Map */
#define TTSA			0x001c		/* TX Time Slot Assignment Register */
#define  TCC			0x00000001	/* Transmit Channel Capacity */
#define  TEPCM			0x00008000	/* Enable PCM Mask Transmit */
#define  TCS			0x00010000	/* Transmit Clock Shift */
#define  TTSN			0x01000000	/* Transmit Time Slot Number */
#define RTSA			0x0020		/* RX Time Slot Assignment Register */
#define  RCC			0x00000001	/* Receive Channel Capacity */
#define  REPCM			0x00008000	/* Enable PCM Mask Receive */
#define  RCS			0x00010000	/* Receive Clock Shift */
#define  RTSN			0x01000000	/* Receive Time Slot Number */
#define PCMMTX			0x0024		/* PCM Mask for Transmit */
#define PCMMRX			0x0028		/* PCM Mask for Receive */
#define BRR				0x002c		/* Baud Rate Register */
#define  BRN			0x00000001	/* Baud Rate Factor N */
#define  BRM			0x00000100	/* Baud Rate Factor M   k=(N+1)*2^M */
#define TIMR			0x0030		/* Timer Register */
#define  TVALUE			0x00000001	/* Timer Expiration Value */
#define  CNT			0x01000000	/* Counter */
#define  TMD			0x10000000	/* Timer Mode */
#define  SRC			0x80000000	/* Clock Source */
#define XADR			0x0034		/* TX Address Register */
#define  XAD1			0x00000001	/* Transmit Address 1 */
#define  XAD2			0x00000100	/* Transmit Address 2 */
#define RADR			0x0038		/* RX Address Register */
#define  RAL1			0x00010000	/* RX Address 1 Low-Byte */
#define  RAH1			0x01000000	/* RX Address 1 High-Byte */
#define  RAL2			0x00000001	/* RX Address 2 Low-Byte */
#define  RAH2			0x00000100	/* RX Address 2 High-Byte */
#define RAMR			0x003c		/* Receive Address Mask Register */
#define  AMRAL1			0x00000001	/* Receive Mask Address 1 Low-Byte */
#define  AMRAH1			0x00000100	/* Receive Mask Address 1 High-Byte */
#define  AMRAL2			0x00010000	/* Receive Mask Address 2 Low-Byte */
#define  AMRAH2			0x01000000	/* Receive Mask Address 2 High-Byte */
#define RLCR			0x0040		/* Receive Length Check Register */
#define  RL				0x00000001	/* Receive Length Check Limit */
#define  RCE			0x00008000	/* Receive Length Check Enable */
#define XNXFR			0x0044		/* XON/XOFF Register */
#define  MXOFF			0x00000001	/* XOFF Character Mask */
#define  MXON			0x00000100	/* XON Character Mask */
#define  CXOFF			0x00010000	/* XOFF Character */
#define  CXON			0x01000000	/* XON Character */
#define TCR				0x0048		/* Termination Character Register */
#define  TC				0x00000001	/* Termination Character */
#define  TCDE			0x00008000	/* Termination Character Detection Enable */
#define TICR			0x004c		/* Transmit Immediate Character Register */
#define SYNCR			0x0050		/* Synchronization Character Register */
#define  SYNCL			0x00000001	/* Synchronization Character Low */
#define  SYNCH			0x00000100	/* Synchronization Character High */
#define IMR				0x0054		/* Interrupt Mask Register */
#define ISR				0x0058		/* Interrupt Status Register */
#define  FLEX			0x00000001	/* Frame Length Exceeded Interrupt */
#define  RFO			0x00000002	/* RX FIFO Overflow Interrupt */
#define  CDSC			0x00000004	/* Carrier Detect Status Change Interrupt */
#define  PLLA			0x00000008	/* DPLL Asynchronous Interrupt */
#define  PCE			0x00000010	/* Protocol Error Interrupt */
#define  FERR			0x00000010	/* Framing Error Interrupt */
#define  SCD			0x00000010	/* SYN Character Detected Interrupt */
#define  RSC			0x00000020	/* Receive Status Change Interrupt */
#define  PERR			0x00000020	/* Parity Error Interrupt */
#define  RFS			0x00000040	/* Receive Frame Start Interrupt */
#define  TOUT			0x00000040	/* Time Out Interrupt */
#define  RDO			0x00000080	/* Receive Data Overflow Interrupt */
#define  TCD			0x00000080	/* Termination Character Detected Interrupt */
#define  BRKT			0x00000100	/* Break Terminated Interrupt */
#define  BRK			0x00000200	/* Break Interrupt */
#define  XPR			0x00001000	/* Transmit Pool Ready Interrupt */