pciscc.h

高速同步串口芯片PEB20534的驱动程序

#define  SRC		0x80000000	/* Clock Source */
#define XADR		0x0034		/* TX Address Register */
#define  XAD1		0x00000001	/* Transmit Address 1 */
#define  XAD2		0x00000100	/* Transmit Address 2 */
#define RADR		0x0038		/* RX Address Register */
#define  RAL1		0x00010000	/* RX Address 1 Low-Byte */
#define  RAH1		0x01000000	/* RX Address 1 High-Byte */
#define  RAL2		0x00000001	/* RX Address 2 Low-Byte */
#define  RAH2		0x00000100	/* RX Address 2 High-Byte */
#define RAMR		0x003c		/* Receive Address Mask Register */
#define  AMRAL1		0x00000001	/* Receive Mask Address 1 Low-Byte */
#define  AMRAH1		0x00000100	/* Receive Mask Address 1 High-Byte */
#define  AMRAL2		0x00010000	/* Receive Mask Address 2 Low-Byte */
#define  AMRAH2		0x01000000	/* Receive Mask Address 2 High-Byte */
#define RLCR		0x0040		/* Receive Length Check Register */
#define  RL		0x00000001	/* Receive Length Check Limit */
#define  RCE		0x00008000	/* Receive Length Check Enable */
#define XNXFR		0x0044		/* XON/XOFF Register */
#define  MXOFF		0x00000001	/* XOFF Character Mask */
#define  MXON		0x00000100	/* XON Character Mask */
#define  CXOFF		0x00010000	/* XOFF Character */
#define  CXON		0x01000000	/* XON Character */
#define TCR		0x0048		/* Termination Character Register */
#define  TC		0x00000001	/* Termination Character */
#define  TCDE		0x00008000	/* Termination Character Detection Enable */
#define TICR		0x004c		/* Transmit Immediate Character Register */
#define SYNCR		0x0050		/* Synchronization Character Register */
#define  SYNCL		0x00000001	/* Synchronization Character Low */
#define  SYNCH		0x00000100	/* Synchronization Character High */
#define IMR		0x0054		/* Interrupt Mask Register */
#define ISR		0x0058		/* Interrupt Status Register */
#define  FLEX		0x00000001	/* Frame Length Exceeded Interrupt */
#define  RFO		0x00000002	/* RX FIFO Overflow Interrupt */
#define  CDSC		0x00000004	/* Carrier Detect Status Change Interrupt */
#define  PLLA		0x00000008	/* DPLL Asynchronous Interrupt */
#define  PCE		0x00000010	/* Protocol Error Interrupt */
#define  FERR		0x00000010	/* Framing Error Interrupt */
#define  SCD		0x00000010	/* SYN Character Detected Interrupt */
#define  RSC		0x00000020	/* Receive Status Change Interrupt */
#define  PERR		0x00000020	/* Parity Error Interrupt */
#define  RFS		0x00000040	/* Receive Frame Start Interrupt */
#define  TIME		0x00000040	/* Time Out Interrupt */
#define  RDO		0x00000080	/* Receive Data Overflow Interrupt */
#define  TCD		0x00000080	/* Termination Character Detected Interrupt */
#define  BRKT		0x00000100	/* Break Terminated Interrupt */
#define  BRK		0x00000200	/* Break Interrupt */
#define  XPR		0x00001000	/* Transmit Pool Ready Interrupt */
#define  XMR		0x00002000	/* Transmit Message Repeat */
#define  XON		0x00002000	/* XOFF Character Detected Interrupt */
#define  CSC		0x00004000	/* /CTS Status Change */
#define  TIN		0x00008000	/* Timer Interrupt */
#define  XDU		0x00010000	/* Transmit Data Underrun Interrupt */
#define  ALLS		0x00040000	/* All Sent Interrupt */

/* Peripheral control registers */
#define LCONF		0x0300		/* LBI Configuration Register */
#define  MCTC		0x00000001	/* LBI Memory Cycle Time Control */
#define  ABM		0x00000010	/* LBI Arbitration Master */
#define  RDEN		0x00000020	/* LBI LRDY Enable */
#define  BTYP		0x00000040	/* LBI Bus Type */
#define  BTYP0		0x00000040
#define  BTYP1		0x00000080
#define  HDEN		0x00000100	/* LBI HOLD Enable */
#define  EALE		0x00000200	/* LBI Extended ALE */
#define  EBCRES		0x00400000	/* LBI External Bus Controller Reset */
#define  LINTIC		0x80000000	/* LBI Interrupt Input Control */
#define SSCCON		0x0380		/* SSC Control Register */
#define  SSCBM		0x00000001	/* SSC Data Width Control */
#define  SSCBC		0x00000001	/* SSC Shift Counter */
#define  SSCHB		0x00000010	/* SSC Heading (Bit Order) Control */
#define  SSCPH		0x00000020	/* SSC Clock Phase Control */
#define  SSCPO		0x00000040	/* SSC Polarity Control */
#define  SSCTEN		0x00000100	/* SSC Transmit Error Enable */
#define  SSCTE		0x00000100	/* SSC Transmit Status Flag */
#define  SSCREN		0x00000200	/* SSC Receive Error Enable */
#define  SSCRE		0x00000200	/* SSC Receive Status Flag */
#define  SSCPEN		0x00000400	/* SSC Phase Error Enable */
#define  SSCPE		0x00000400	/* SSC Baud Rate Status Flag */
#define  SSCBEN		0x00000800	/* SSC Baud Rate Error Enable */
#define  SSCBE		0x00000800	/* SSC Baud Rate Status Flag */
#define  SSCBSY		0x00001000	/* SSC Busy Flag */
#define  SSCMS		0x00004000	/* SSC Master Select */
#define  SSCEN		0x00008000	/* SSC Enable */
#define SSCBR		0x0384		/* SSC Baud Rate Generator Register */
#define SSCTB		0x0388		/* SSC Transmit Buffer */
#define SSCRB		0x038c		/* SSC Receive Buffer */
#define SSCCSE		0x0390		/* SSC Chip Select Enable Register */
#define  ASEL0		0x00000010	/* SSC Chipselect 0 */
#define  ASEL1		0x00000020	/* SSC Chipselect 1 */
#define  ASEL2		0x00000040	/* SSC Chipselect 2 */
#define  ASEL3		0x00000080	/* SSC Chipselect 3 */
#define SSCIM		0x0394		/* SSC Interrupt Mask Register */
#define  IMTX		0x00000001	/* SSC Transmit Interrupt Mask */
#define  IMER		0x00000002	/* SSC Error Interrupt Mask */
#define  IMRX		0x00000004	/* SSC Receive Interrupt Mask */
#define GPDIR		0x0400		/* GPP Direction Configuration Register */
#define GPDATA		0x0404		/* GPP Data I/O Register */
#define GPIM		0x0408		/* GPP Interrupt Mask Register */

/* Receive Data Section Status Byte (HDLC mode) */
#define SB_LA		0x00000001	/* low byte address compare */
#define SB_CR		0x00000002	/* command/response */
#define SB_HA0		0x00000004	/* high byte address compare */
#define SB_HA1		0x00000008
#define SB_RAB		0x00000010	/* receive message aborted */
#define SB_CRC		0x00000020	/* CRC compare */
#define SB_RDO		0x00000040	/* receive data overflow */
#define SB_VFR		0x00000080	/* valid frame */

/* Configuration Interrupt Vector */
#define CIV_ARACK	0x00000001	/* action request acknowledge */
#define CIV_ARF		0x00000002	/* action request failed */
#define	CIV_SRCID	0x10000000	/* source ID, always 0x0a */
#define CIV_SRCIDVAL	0x0a

/* DMA Controller Interrupt Vector */
#define DMACIV_ERR	0x00010000	/* error indication interrupt */
#define DMACIV_FI	0x00020000	/* frame indication interrupt */
#define DMACIV_HI	0x00040000	/* host initiated interrupt */
#define DMACIV_SRCID	0x10000000

/* SCC Interrupt Vector */
#define SCCIV_FLEX	0x00000001	/* Frame Length Exceeded Interrupt */
#define SCCIV_RFO	0x00000002	/* RX FIFO Overflow Interrupt */
#define SCCIV_CDSC	0x00000004	/* Carrier Detect Status Change Interrupt */
#define SCCIV_PLLA	0x00000008	/* DPLL Asynchronous Interrupt */
#define SCCIV_PCE	0x00000010	/* Protocol Error Interrupt */
#define SCCIV_FERR	0x00000010	/* Framing Error Interrupt */
#define SCCIV_SCD	0x00000010	/* SYN Character Detected Interrupt */
#define SCCIV_RSC	0x00000020	/* Receive Status Change Interrupt */
#define SCCIV_PERR	0x00000020	/* Parity Error Interrupt */
#define SCCIV_RFS	0x00000040	/* Receive Frame Start Interrupt */
#define SCCIV_TIME	0x00000040	/* Time Out Interrupt */
#define SCCIV_RDO	0x00000080	/* Receive Data Overflow Interrupt */
#define SCCIV_TCD	0x00000080	/* Termination Character Detected Interrupt */
#define SCCIV_BRKT	0x00000100	/* Break Terminated Interrupt */
#define SCCIV_BRK	0x00000200	/* Break Interrupt */
#define SCCIV_XPR	0x00001000	/* Transmit Pool Ready Interrupt */
#define SCCIV_XMR	0x00002000	/* Transmit Message Repeat */
#define SCCIV_XOFF	0x00002000	/* XOFF Character Detected Interrupt */
#define SCCIV_CSC	0x00004000	/* /CTS Status Change */
#define SCCIV_TIN	0x00008000	/* Timer Interrupt */
#define SCCIV_XDU	0x00010000	/* Transmit Data Underrun Interrupt */
#define SCCIV_ALLS	0x00040000	/* All Sent Interrupt */
#define SCCIV_SRCID	0x10000000
#define SCCIV_SCC	0x02000000	/* 1: SCC generated. 0: DMAC generated */
#define SCCIV_ERR	0x00010000	/* ERROR Indication Interrupt */
#define SCCIV_FI	0x00020000	/* Frame Indication Interrupt */
#define SCCIV_HI	0x00040000	/* Host Initiated Interrupt */
#define SCCIV_IGNORE	0x00100000	/* internal use */

/* SSC Interrupt Vector */
#define SSCIV_INSW	0x00000001	/* interrupt status word */
#define SSCIV_TX	0x00010000	/* transmit interrupt */
#define SSCIV_RX	0x00020000	/* receive interrupt */
#define SSCIV_ERR	0x00040000	/* error interrupt */
#define SSCIV_DE	0x00800000	/* data/error indication */
#define SSCIV_RT	0x01000000	/* rx/tx indicator */
#define SSCIV_SRCID	0x10000000
#define SSCIV_SRCIDVAL	0x0c

/* LBI Interrupt Vector */
#define LBIIV_SRCID	0x10000000
#define LBIIV_SRCIDVAL	0x0d

/* GPP Interrupt Vector */
#define GPPIV_GPDATA	0x00000001
#define GPPIV_SRCID	0x10000000
#define GPPIV_SRCIDVAL	0x0f

struct frame_t {					/* L1 frame pool element */
	L1FRAME			l1_frame;
	unsigned int		valid;
	unsigned int		reserved;
};

struct tx_desc_t {
	unsigned long		flags;
#define NO	0x00010000				/* number of bytes */
#define HI	0x20000000				/* host initiated interrupt */
#define HOLD	0x40000000				/* last descriptor in chain */
#define FE	0x80000000				/* frame end */
	unsigned long		nextptr;
	unsigned long		dataptr;
	unsigned long		result;
#define C	0x40000000				/* descriptor complete flag */
	L1FRAME far		*l1_frame;		/* pointer to frame buffer */
	struct tx_desc_t	*next;			/* note virtaddr */
	struct tx_desc_t	*prev;
};

struct rx_desc_t {
	unsigned long		flags;
#define RA	0x00000200				/* receive abort */
	unsigned long		nextptr;		/* note busaddr */
	unsigned long		dataptr;
	unsigned long		result;
	unsigned long		feptr;
	L1FRAME far		*l1_frame;		/* pointer to frame buffer */
	struct rx_desc_t	*next;			/* note virtaddr */
	struct rx_desc_t	*prev;			/* previous */
};

struct buffer_t {
	unsigned long		iq_per[CFG_IQLEN];	/* IQ_PER/IQ_CFG buffer */
	unsigned long		iq_cfg[CFG_IQLEN];
	unsigned long		iq_rx[4][CFG_IQLEN];	/* IQ_RX/IQ_TX buffer */
	unsigned long		iq_tx[4][CFG_IQLEN];
	struct rx_desc_t	dq_rx[4][CFG_RX_DESC];	/* RX/TX descriptors */
	struct tx_desc_t	dq_tx[4][CFG_TX_DESC];
	struct frame_t		frm_pool[CFG_L1_BUF];	/* RX/TX frame buffers */
	unsigned char		dummy[260];
};

struct devctl_t {
	L1_STATISTICS		stats;			/* statistics */
	unsigned int		initialized;		/* channel initialized? */
	unsigned long		*iq_rx;			/* interrupt queues */
	unsigned long		*iq_tx;
	unsigned long		*iq_rx_next;		/* next entry to be processed */
	unsigned long		*iq_tx_next;
	struct rx_desc_t	*dq_rx;			/* RX descriptor queue */
	struct rx_desc_t	*dq_rx_next;
	struct tx_desc_t	*dq_tx;			/* TX descriptor queue */
	struct tx_desc_t	*dq_tx_last;
	struct tx_desc_t	*dq_tx_cleanup;
	unsigned int		tx_enqueued;
	unsigned long		bitrate;		/* effective bitrate */
	unsigned int		mode;			/* mode flags */
	unsigned int		scale;
	volatile unsigned int	txstate;
	volatile unsigned long	rx_mailbox;		/* communication with isr */
	volatile unsigned long	tx_mailbox;		/* communication with isr */
	unsigned long		ccr0;			/* SCC register contents */
	unsigned long		ccr1;
	unsigned long		ccr2;
};

struct chipctl_t {
	unsigned long		*iq_per;		/* peripheral interrupt queue */
	unsigned long		*iq_cfg;		/* configuration interrupt queue */
	unsigned long		*iq_per_next;		/* next entry to be processed */
	unsigned long		*iq_cfg_next;
	unsigned char		card_num;
	unsigned long		io_base;
	unsigned char		irq;
	unsigned char		oldpic[2];
	void interrupt		(*oldvect)(void);	/* old interrupt vector */
	unsigned int		initialized;		/* chip initialized? */
	unsigned int		txd_scale;		/* tx delay scaling */
	volatile unsigned int	mailbox;		/* communication with isr */
#define MAILBOX_NONE	0
#define MAILBOX_OK	1
#define MAILBOX_FAILURE	2
	struct buffer_t		*dma_buffers;		/* chip communication buffers */
	L1FRAME far		*rx_queue[CFG_L1_BUF];	/* RX frame queue */
	L1FRAME far		**rx_put;
	L1FRAME far		**rx_get;
};

#define	TX_RESET	0
#define TX_IDLE		1
#define	TX_DELAY	2
#define	TX_XMIT		3
#define TX_TAIL		4
#define TX_CAL		5
#define	TX_STALL	6

/* function prototypes */
int	pciscc_chip_init(void);
int	pciscc_chip_open(void);
void	pciscc_chip_close(void);
int	pciscc_channel_open(int chan, long bitrate, int mode);
void	pciscc_channel_close(int chan);
void interrupt	pciscc_isr(void);
void	pciscc_isr_receiver(int chan);
void	pciscc_isr_txcleanup(int chan);

#endif	/* _PCISCC_H_ */