uart_rx_tb.vhd

lattice的串口仿真的程序

    -- Test 18 ---------------------------------------------------
    --   8-bit data receiving test, stick even parity
    wait until rising_edge(okToReceiveSIN);
    sin_gen(8,"10101010",'0',1.0,true,true,CLK_PERIOD*16, SIN);
    sin_gen(8,"01010110",'0',1.0,true,true,CLK_PERIOD*16, SIN);

    -- Test 19 ---------------------------------------------------
    --   8-bit data receiving test, stick odd parity
    wait until rising_edge(okToReceiveSIN);
    sin_gen(8,"10101010",'1',1.0,true,true,CLK_PERIOD*16, SIN);
    sin_gen(8,"01010110",'1',1.0,true,true,CLK_PERIOD*16, SIN);

    -- Test 20 ---------------------------------------------------
    --   8-bit data receiving test, no parity
    wait until rising_edge(okToReceiveSIN);
    sin_gen(8,"10101010",'0',1.0,false,true,CLK_PERIOD*16, SIN);
    sin_gen(8,"01010110",'0',1.0,false,true,CLK_PERIOD*16, SIN);


    -- end of tests ----------------------------------------------
    wait;

  end process SIN_proc;


-----------------------------------------------------------------------
-- Test UART Transmitter/Receiver Functions
-----------------------------------------------------------------------
  UART_Stim_Proc : process
    variable i : integer;
  begin

    -- Reset and Intialization
    MR <= '1';

    CS <= '0';
    ADSn <= '1';
    A <= "111";
    DIN <= "11111111";

    CTSn <= '1';
    DCDn <= '1';
    DSRn <= '1';
    RIn  <= '1';

    wait for (9.5*CLK_PERIOD);

    MR <= '0';

    wait for (0.5*CLK_PERIOD);


    wait until falling_edge(PCLK);
    -- Test 1 ----------------------------------------------------
    --   5-bit data receiving test, even parity
    TestID <= 1;

    -- IER Intialization
    --   bit 3 : 0, disable modem status interrupt
    --   bit 2 : 0, disable receiver line status interrupt
    --   bit 1 : 0, disable tranmitter holding register empty interrupt
    --   bit 0 : 1, enable received data available interrupt
    write_reg (IER,"00000001",CS,ADSn,WRn,A,DIN);

    -- LCR Intialization
    --   bit 6 : 0, do not set break
    --   bit 5 : 0, not stick parity
    --   bit 4 : 1, even parity selected
    --   bit 3 : 1, parity enabled
    --   bit 2 : 0, 1 stop bit
    --   bit 1 : 0, 5 data bit (bit[1-0]="00")
    --   bit 0 : 0, 5 data bit (bit[1-0]="00")
    write_reg (LCR,"00011000",CS,ADSn,WRn,A,DIN);

    -- trigger okToReceiveSIN to get character from SIN
    okToReceiveSIN <= '1',
                      '0' after 1 ns;

    -- Wait for INTR high
    i := 1;
    loop
      if (i < WAIT_TIMEOUT) then
        wait for CLK_PERIOD;
        exit when INTR = '1';
        i := i + 1;
      else
        assert (false) report"Interrupt Generation Failed"
        severity failure;
      end if;
    end loop;

    -- Read and check LSR (check if "Data Ready" flag at bit 0 is set)
    read_reg (LSR,regData_readBack,CS,ADSn,RDn,A,DOUT);
    assert regData_readBack = "01100001"
      report"Invalid LSR"
      severity failure;

    -- Read and check LSR (read again to see if it's changed by LSR read)
    read_reg (LSR,regData_readBack,CS,ADSn,RDn,A,DOUT);
    assert regData_readBack = "01100001"
      report"Invalid LSR"
      severity failure;

    -- Check if INTR is still high
    assert INTR = '1'
      report"Interrupt negated"
      severity failure;

    -- Read and check RBR
    read_reg (RBR,regData_readBack,CS,ADSn,RDn,A,DOUT);
    assert regData_readBack = "00001010"
      report"Invalid RBR"
      severity failure;

    -- Check if INTR is low
    wait for CLK_PERIOD;
    assert INTR = '0'
      report"Interrupt not negated"
      severity failure;

    -- Read and check LSR (check if "Data Ready" flag at bit 0 is cleared)
    read_reg (LSR,regData_readBack,CS,ADSn,RDn,A,DOUT);
    assert regData_readBack = "01100000"
      report"Invalid LSR"
      severity failure;

    -- Wait for INTR high
    i := 1;
    loop
      if (i < WAIT_TIMEOUT) then
        wait for CLK_PERIOD;
        exit when INTR = '1';
        i := i + 1;
      else
        assert (false) report"Interrupt Generation Failed"
        severity failure;
      end if;
    end loop;

    -- Check if INTR is still high
    assert INTR = '1'
      report"Interrupt negated"
      severity failure;

    -- Read and check RBR
    read_reg (RBR,regData_readBack,CS,ADSn,RDn,A,DOUT);
    assert regData_readBack = "00010110"
      report"Invalid RBR"
      severity failure;

    -- Check if INTR is low
    wait for CLK_PERIOD;
    assert INTR = '0'
      report"Interrupt not negated"
      severity failure;


    wait until falling_edge(PCLK);
    -- Test 2 ----------------------------------------------------
    --   5-bit data receiving test, odd parity
    TestID <= 2;

    -- IER Intialization
    --   bit 3 : 0, disable modem status interrupt
    --   bit 2 : 0, disable receiver line status interrupt
    --   bit 1 : 0, disable tranmitter holding register empty interrupt
    --   bit 0 : 1, enable received data available interrupt
    write_reg (IER,"00000001",CS,ADSn,WRn,A,DIN);

    -- LCR Intialization
    --   bit 6 : 0, do not set break
    --   bit 5 : 0, not stick parity
    --   bit 4 : 0, odd parity selected
    --   bit 3 : 1, parity enabled
    --   bit 2 : 0, 1 stop bit
    --   bit 1 : 0, 5 data bit (bit[1-0]="00")
    --   bit 0 : 0, 5 data bit (bit[1-0]="00")
    write_reg (LCR,"00001000",CS,ADSn,WRn,A,DIN);

    -- trigger okToReceiveSIN to get character from SIN
    okToReceiveSIN <= '1',
                      '0' after 1 ns;

    -- Wait for INTR high
    i := 1;
    loop
      if (i < WAIT_TIMEOUT) then
        wait for CLK_PERIOD;
        exit when INTR = '1';
        i := i + 1;
      else
        assert (false) report"Interrupt Generation Failed"
        severity failure;
      end if;
    end loop;

    -- Read and check LSR (check if "Data Ready" flag at bit 0 is set)
    read_reg (LSR,regData_readBack,CS,ADSn,RDn,A,DOUT);
    assert regData_readBack = "01100001"
      report"Invalid LSR"
      severity failure;

    -- Read and check LSR (read again to see if it's changed by LSR read)
    read_reg (LSR,regData_readBack,CS,ADSn,RDn,A,DOUT);
    assert regData_readBack = "01100001"
      report"Invalid LSR"
      severity failure;

    -- Check if INTR is still high
    assert INTR = '1'
      report"Interrupt negated"
      severity failure;

    -- Read and check RBR
    read_reg (RBR,regData_readBack,CS,ADSn,RDn,A,DOUT);
    assert regData_readBack = "00001010"
      report"Invalid RBR"
      severity failure;

    -- Check if INTR is low
    wait for CLK_PERIOD;
    assert INTR = '0'
      report"Interrupt not negated"
      severity failure;

    -- Read and check LSR (check if "Data Ready" flag at bit 0 is cleared)
    read_reg (LSR,regData_readBack,CS,ADSn,RDn,A,DOUT);
    assert regData_readBack = "01100000"
      report"Invalid LSR"
      severity failure;

    -- Wait for INTR high
    i := 1;
    loop
      if (i < WAIT_TIMEOUT) then
        wait for CLK_PERIOD;
        exit when INTR = '1';
        i := i + 1;
      else
        assert (false) report"Interrupt Generation Failed"
        severity failure;
      end if;
    end loop;

    -- Check if INTR is still high
    assert INTR = '1'
      report"Interrupt negated"
      severity failure;

    -- Read and check RBR
    read_reg (RBR,regData_readBack,CS,ADSn,RDn,A,DOUT);
    assert regData_readBack = "00010110"
      report"Invalid RBR"
      severity failure;

    -- Check if INTR is low
    wait for CLK_PERIOD;
    assert INTR = '0'
      report"Interrupt not negated"
      severity failure;


    wait until falling_edge(PCLK);
    -- Test 3 ----------------------------------------------------
    --   5-bit data receiving test, stick even parity
    TestID <= 3;

    -- IER Intialization
    --   bit 3 : 0, disable modem status interrupt
    --   bit 2 : 0, disable receiver line status interrupt
    --   bit 1 : 0, disable tranmitter holding register empty interrupt
    --   bit 0 : 1, enable received data available interrupt
    write_reg (IER,"00000001",CS,ADSn,WRn,A,DIN);

    -- LCR Intialization
    --   bit 6 : 0, do not set break
    --   bit 5 : 1, stick parity
    --   bit 4 : 1, even parity selected
    --   bit 3 : 1, parity enabled
    --   bit 2 : 0, 1 stop bit
    --   bit 1 : 0, 5 data bit (bit[1-0]="00")
    --   bit 0 : 0, 5 data bit (bit[1-0]="00")
    write_reg (LCR,"00111000",CS,ADSn,WRn,A,DIN);

    -- trigger okToReceiveSIN to get character from SIN
    okToReceiveSIN <= '1',
                      '0' after 1 ns;

    -- Wait for INTR high
    i := 1;
    loop
      if (i < WAIT_TIMEOUT) then
        wait for CLK_PERIOD;
        exit when INTR = '1';
        i := i + 1;
      else
        assert (false) report"Interrupt Generation Failed"
        severity failure;
      end if;
    end loop;

    -- Read and check LSR (check if "Data Ready" flag at bit 0 is set)
    read_reg (LSR,regData_readBack,CS,ADSn,RDn,A,DOUT);
    assert regData_readBack = "01100001"
      report"Invalid LSR"
      severity failure;

    -- Read and check LSR (read again to see if it's changed by LSR read)
    read_reg (LSR,regData_readBack,CS,ADSn,RDn,A,DOUT);
    assert regData_readBack = "01100001"
      report"Invalid LSR"
      severity failure;

    -- Check if INTR is still high
    assert INTR = '1'
      report"Interrupt negated"
      severity failure;

    -- Read and check RBR
    read_reg (RBR,regData_readBack,CS,ADSn,RDn,A,DOUT);
    assert regData_readBack = "00001010"
      report"Invalid RBR"
      severity failure;

    -- Check if INTR is low
    wait for CLK_PERIOD;
    assert INTR = '0'
      report"Interrupt not negated"
      severity failure;

    -- Read and check LSR (check if "Data Ready" flag at bit 0 is cleared)
    read_reg (LSR,regData_readBack,CS,ADSn,RDn,A,DOUT);
    assert regData_readBack = "01100000"
      report"Invalid LSR"
      severity failure;

    -- Wait for INTR high
    i := 1;
    loop
      if (i < WAIT_TIMEOUT) then
        wait for CLK_PERIOD;
        exit when INTR = '1';
        i := i + 1;
      else
        assert (false) report"Interrupt Generation Failed"
        severity failure;
      end if;
    end loop;

    -- Check if INTR is still high
    assert INTR = '1'
      report"Interrupt negated"
      severity failure;

    -- Read and check RBR
    read_reg (RBR,regData_readBack,CS,ADSn,RDn,A,DOUT);
    assert regData_readBack = "00010110"
      report"Invalid RBR"
      severity failure;

    -- Check if INTR is low
    wait for CLK_PERIOD;
    assert INTR = '0'
      report"Interrupt not negated"
      severity failure;


    wait until falling_edge(PCLK);
    -- Test 4 ----------------------------------------------------
    --   5-bit data receiving test, stick odd parity
    TestID <= 4;

    -- IER Intialization
    --   bit 3 : 0, disable modem status interrupt
    --   bit 2 : 0, disable receiver line status interrupt
    --   bit 1 : 0, disable tranmitter holding register empty interrupt
    --   bit 0 : 1, enable received data available interrupt
    write_reg (IER,"00000001",CS,ADSn,WRn,A,DIN);

    -- LCR Intialization
    --   bit 6 : 0, do not set break
    --   bit 5 : 1, stick parity
    --   bit 4 : 0, odd parity selected
    --   bit 3 : 1, parity enabled
    --   bit 2 : 0, 1 stop bit
    --   bit 1 : 0, 5 data bit (bit[1-0]="00")
    --   bit 0 : 0, 5 data bit (bit[1-0]="00")
    write_reg (LCR,"00101000",CS,ADSn,WRn,A,DIN);

    -- trigger okToReceiveSIN to get character from SIN
    okToReceiveSIN <= '1',
                      '0' after 1 ns;

    -- Wait for INTR high
    i := 1;
    loop
      if (i < WAIT_TIMEOUT) then
        wait for CLK_PERIOD;
        exit when INTR = '1';
        i := i + 1;
      else
        assert (false) report"Interrupt Generation Failed"
        severity failure;
      end if;
    end loop;

    -- Read and check LSR (check if "Data Ready" flag at bit 0 is set)
    read_reg (LSR,regData_readBack,CS,ADSn,RDn,A,DOUT);
    assert regData_readBack = "01100001"
      report"Invalid LSR"
      severity failure;

    -- Read and check LSR (read again to see if it's changed by LSR read)