📄 uart_tx_tb.vhd

📁 lattice的串口仿真的程序
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    --   bit 5 : 1, stick parity
    --   bit 4 : 0, odd parity selected
    --   bit 3 : 1, parity enabled
    --   bit 2 : 0, 1 stop bit
    --   bit 1 : 0, 6 data bit (bit[1-0]="01")
    --   bit 0 : 1, 6 data bit (bit[1-0]="01")
    write_reg (LCR,"00101001",CS,ADSn,WRn,A,DIN);

    -- Write 1st data to THR
    write_reg (THR,"01010101",CS,ADSn,WRn,A,DIN);

    -- Write 2nd data to THR
    if (TxRDYn = '1') then
       wait until TxRDYn = '0';
    end if;
    write_reg (THR,"10101010",CS,ADSn,WRn,A,DIN);

    -- Write 3rd data to THR
    if (TxRDYn = '1') then
       wait until TxRDYn = '0';
    end if;
    write_reg (THR,"01011010",CS,ADSn,WRn,A,DIN);

    -- Write 4th data to THR
    if (TxRDYn = '1') then
       wait until TxRDYn = '0';
    end if;
    write_reg (THR,"10100101",CS,ADSn,WRn,A,DIN);


    wait until falling_edge(PCLK);
    -- Test 18;---------------------------------------------------
    --   6-bit data, stick odd parity, 2 stop
    TestID <= 18;

    i := 1;
    loop
      if (i < WAIT_TIMEOUT) then
        wait for CLK_PERIOD;
        -- Read LSR (check if "TEMT" flag at bit 6 is set)
        read_reg (LSR,regData_readBack,CS,ADSn,RDn,A,DOUT);
        exit when regData_readBack(6) = '1';
        i := i + 1;
      else
        assert (false) report"Data Transmission Failed"
        severity failure;
      end if;
    end loop;
    wait for (16*CLK_PERIOD);

    -- LCR Intialization
    --   bit 6 : 0, do not set break
    --   bit 5 : 1, stick parity
    --   bit 4 : 0, odd parity selected
    --   bit 3 : 1, parity enabled
    --   bit 2 : 1, 2 stop bit
    --   bit 1 : 0, 6 data bit (bit[1-0]="01")
    --   bit 0 : 1, 6 data bit (bit[1-0]="01")
    write_reg (LCR,"00101101",CS,ADSn,WRn,A,DIN);

    -- Write 1st data to THR
    write_reg (THR,"01010101",CS,ADSn,WRn,A,DIN);

    -- Write 2nd data to THR
    if (TxRDYn = '1') then
       wait until TxRDYn = '0';
    end if;
    write_reg (THR,"10101010",CS,ADSn,WRn,A,DIN);

    -- Write 3rd data to THR
    if (TxRDYn = '1') then
       wait until TxRDYn = '0';
    end if;
    write_reg (THR,"01011010",CS,ADSn,WRn,A,DIN);

    -- Write 4th data to THR
    if (TxRDYn = '1') then
       wait until TxRDYn = '0';
    end if;
    write_reg (THR,"10100101",CS,ADSn,WRn,A,DIN);


    wait until falling_edge(PCLK);
    -- Test 19 ---------------------------------------------------
    --   6-bit data, no parity, 1 stop
    TestID <= 19;

    i := 1;
    loop
      if (i < WAIT_TIMEOUT) then
        wait for CLK_PERIOD;
        -- Read LSR (check if "TEMT" flag at bit 6 is set)
        read_reg (LSR,regData_readBack,CS,ADSn,RDn,A,DOUT);
        exit when regData_readBack(6) = '1';
        i := i + 1;
      else
        assert (false) report"Data Transmission Failed"
        severity failure;
      end if;
    end loop;
    wait for (16*CLK_PERIOD);

    -- LCR Intialization
    --   bit 6 : 0, do not set break
    --   bit 5 : 0, not stick parity
    --   bit 4 : 0, odd parity selected
    --   bit 3 : 0, parity disabled
    --   bit 2 : 0, 1 stop bit
    --   bit 1 : 0, 6 data bit (bit[1-0]="01")
    --   bit 0 : 1, 6 data bit (bit[1-0]="01")
    write_reg (LCR,"00000001",CS,ADSn,WRn,A,DIN);

    -- Write 1st data to THR
    write_reg (THR,"01010101",CS,ADSn,WRn,A,DIN);

    -- Write 2nd data to THR
    if (TxRDYn = '1') then
       wait until TxRDYn = '0';
    end if;
    write_reg (THR,"10101010",CS,ADSn,WRn,A,DIN);

    -- Write 3rd data to THR
    if (TxRDYn = '1') then
       wait until TxRDYn = '0';
    end if;
    write_reg (THR,"01011010",CS,ADSn,WRn,A,DIN);

    -- Write 4th data to THR
    if (TxRDYn = '1') then
       wait until TxRDYn = '0';
    end if;
    write_reg (THR,"10100101",CS,ADSn,WRn,A,DIN);


    wait until falling_edge(PCLK);
    -- Test 20 ---------------------------------------------------
    --   6-bit data, stick odd parity, 2 stop
    TestID <= 20;

    i := 1;
    loop
      if (i < WAIT_TIMEOUT) then
        wait for CLK_PERIOD;
        -- Read LSR (check if "TEMT" flag at bit 6 is set)
        read_reg (LSR,regData_readBack,CS,ADSn,RDn,A,DOUT);
        exit when regData_readBack(6) = '1';
        i := i + 1;
      else
        assert (false) report"Data Transmission Failed"
        severity failure;
      end if;
    end loop;
    wait for (16*CLK_PERIOD);

    -- LCR Intialization
    --   bit 6 : 0, do not set break
    --   bit 5 : 0, not stick parity
    --   bit 4 : 0, odd parity selected
    --   bit 3 : 0, parity disabled
    --   bit 2 : 1, 2 stop bit
    --   bit 1 : 0, 6 data bit (bit[1-0]="01")
    --   bit 0 : 1, 6 data bit (bit[1-0]="01")
    write_reg (LCR,"00000101",CS,ADSn,WRn,A,DIN);

    -- Write 1st data to THR
    write_reg (THR,"01010101",CS,ADSn,WRn,A,DIN);

    -- Write 2nd data to THR
    if (TxRDYn = '1') then
       wait until TxRDYn = '0';
    end if;
    write_reg (THR,"10101010",CS,ADSn,WRn,A,DIN);

    -- Write 3rd data to THR
    if (TxRDYn = '1') then
       wait until TxRDYn = '0';
    end if;
    write_reg (THR,"01011010",CS,ADSn,WRn,A,DIN);

    -- Write 4th data to THR
    if (TxRDYn = '1') then
       wait until TxRDYn = '0';
    end if;
    write_reg (THR,"10100101",CS,ADSn,WRn,A,DIN);


    wait until falling_edge(PCLK);
    -- Test 21 ---------------------------------------------------
    --   7-bit data, even parity, 1 stop
    TestID <= 21;

    i := 1;
    loop
      if (i < WAIT_TIMEOUT) then
        wait for CLK_PERIOD;
        -- Read LSR (check if "TEMT" flag at bit 6 is set)
        read_reg (LSR,regData_readBack,CS,ADSn,RDn,A,DOUT);
        exit when regData_readBack(6) = '1';
        i := i + 1;
      else
        assert (false) report"Data Transmission Failed"
        severity failure;
      end if;
    end loop;
    wait for (16*CLK_PERIOD);

    -- LCR Intialization
    --   bit 6 : 0, do not set break
    --   bit 5 : 0, not stick parity
    --   bit 4 : 1, even parity selected
    --   bit 3 : 1, parity enabled
    --   bit 2 : 0, 1 stop bit
    --   bit 1 : 1, 7 data bit (bit[1-0]="10")
    --   bit 0 : 0, 7 data bit (bit[1-0]="10")
    write_reg (LCR,"00011010",CS,ADSn,WRn,A,DIN);

    -- Write 1st data to THR
    write_reg (THR,"01010101",CS,ADSn,WRn,A,DIN);

    -- Write 2nd data to THR
    if (TxRDYn = '1') then
       wait until TxRDYn = '0';
    end if;
    write_reg (THR,"10101010",CS,ADSn,WRn,A,DIN);

    -- Write 3rd data to THR
    if (TxRDYn = '1') then
       wait until TxRDYn = '0';
    end if;
    write_reg (THR,"01011010",CS,ADSn,WRn,A,DIN);

    -- Write 4th data to THR
    if (TxRDYn = '1') then
       wait until TxRDYn = '0';
    end if;
    write_reg (THR,"10100101",CS,ADSn,WRn,A,DIN);


    wait until falling_edge(PCLK);
    -- Test 22 ---------------------------------------------------
    --   7-bit data, even parity, 2 stop
    TestID <= 22;

    i := 1;
    loop
      if (i < WAIT_TIMEOUT) then
        wait for CLK_PERIOD;
        -- Read LSR (check if "TEMT" flag at bit 6 is set)
        read_reg (LSR,regData_readBack,CS,ADSn,RDn,A,DOUT);
        exit when regData_readBack(6) = '1';
        i := i + 1;
      else
        assert (false) report"Data Transmission Failed"
        severity failure;
      end if;
    end loop;
    wait for (16*CLK_PERIOD);

    -- LCR Intialization
    --   bit 6 : 0, do not set break
    --   bit 5 : 0, not stick parity
    --   bit 4 : 1, even parity selected
    --   bit 3 : 1, parity enabled
    --   bit 2 : 1, 2 stop bit
    --   bit 1 : 1, 7 data bit (bit[1-0]="10")
    --   bit 0 : 0, 7 data bit (bit[1-0]="10")
    write_reg (LCR,"00011110",CS,ADSn,WRn,A,DIN);

    -- Write 1st data to THR
    write_reg (THR,"01010101",CS,ADSn,WRn,A,DIN);

    -- Write 2nd data to THR
    if (TxRDYn = '1') then
       wait until TxRDYn = '0';
    end if;
    write_reg (THR,"10101010",CS,ADSn,WRn,A,DIN);

    -- Write 3rd data to THR
    if (TxRDYn = '1') then
       wait until TxRDYn = '0';
    end if;
    write_reg (THR,"01011010",CS,ADSn,WRn,A,DIN);

    -- Write 4th data to THR
    if (TxRDYn = '1') then
       wait until TxRDYn = '0';
    end if;
    write_reg (THR,"10100101",CS,ADSn,WRn,A,DIN);


    wait until falling_edge(PCLK);
    -- Test 23 ---------------------------------------------------
    --   7-bit data, odd parity, 1 stop
    TestID <= 23;

    i := 1;
    loop
      if (i < WAIT_TIMEOUT) then
        wait for CLK_PERIOD;
        -- Read LSR (check if "TEMT" flag at bit 6 is set)
        read_reg (LSR,regData_readBack,CS,ADSn,RDn,A,DOUT);
        exit when regData_readBack(6) = '1';
        i := i + 1;
      else
        assert (false) report"Data Transmission Failed"
        severity failure;
      end if;
    end loop;
    wait for (16*CLK_PERIOD);

    -- LCR Intialization
    --   bit 6 : 0, do not set break
    --   bit 5 : 0, not stick parity
    --   bit 4 : 0, odd parity selected
    --   bit 3 : 1, parity enabled
    --   bit 2 : 0, 1 stop bit
    --   bit 1 : 1, 7 data bit (bit[1-0]="10")
    --   bit 0 : 0, 7 data bit (bit[1-0]="10")
    write_reg (LCR,"00001010",CS,ADSn,WRn,A,DIN);

    -- Write 1st data to THR
    write_reg (THR,"01010101",CS,ADSn,WRn,A,DIN);

    -- Write 2nd data to THR
    if (TxRDYn = '1') then
       wait until TxRDYn = '0';
    end if;
    write_reg (THR,"10101010",CS,ADSn,WRn,A,DIN);

    -- Write 3rd data to THR
    if (TxRDYn = '1') then
       wait until TxRDYn = '0';
    end if;
    write_reg (THR,"01011010",CS,ADSn,WRn,A,DIN);

    -- Write 4th data to THR
    if (TxRDYn = '1') then
       wait until TxRDYn = '0';
    end if;
    write_reg (THR,"10100101",CS,ADSn,WRn,A,DIN);


    wait until falling_edge(PCLK);
    -- Test 24 ---------------------------------------------------
    --   7-bit data, odd parity, 2 stop
    TestID <= 24;

    i := 1;
    loop
      if (i < WAIT_TIMEOUT) then
        wait for CLK_PERIOD;
        -- Read LSR (check if "TEMT" flag at bit 6 is set)
        read_reg (LSR,regData_readBack,CS,ADSn,RDn,A,DOUT);
        exit when regData_readBack(6) = '1';
        i := i + 1;
      else
        assert (false) report"Data Transmission Failed"
        severity failure;
      end if;
    end loop;
    wait for (16*CLK_PERIOD);

    -- LCR Intialization
    --   bit 6 : 0, do not set break
    --   bit 5 : 0, not stick parity
    --   bit 4 : 0, odd parity selected
    --   bit 3 : 1, parity enabled
    --   bit 2 : 1, 2 stop bit
    --   bit 1 : 1, 7 data bit (bit[1-0]="10")
    --   bit 0 : 0, 7 data bit (bit[1-0]="10")
    write_reg (LCR,"00001110",CS,ADSn,WRn,A,DIN);

    -- Write 1st data to THR
    write_reg (THR,"01010101",CS,ADSn,WRn,A,DIN);

    -- Write 2nd data to THR
    if (TxRDYn = '1') then
       wait until TxRDYn = '0';
    end if;
    write_reg (THR,"10101010",CS,ADSn,WRn,A,DIN);

    -- Write 3rd data to THR
    if (TxRDYn = '1') then
上一页 1 2 3 45
💿 文件大小 43 K
👤 上传用户 joyman
📂 所属分类 VHDL/FPGA/Verilog
🏷️ 相关标签

#lattice #串口仿真 #程序
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