dma.ug

~{S2EL~}wdm~{G}6/~}

   If you chose DMARQ5 then you must use DMACK5-, if you chose
   DMARQ6 then you must use DMACK6-, and the same for DMARQ7 and
   DMACK7-.  This determines which 16-bit ISA bus DMA channel
   will be used.

   But the big problem is this:  many of the simple/cheap boards
   don't have the gold tab on the ISA connector for these
   signals.  When I modified a card I had to buy an ATA bus
   "prototype" card that had all the gold tabs on the ISA bus
   connector.  Then I ran the wires from the ATA connector on the
   simple/cheap ATA card to the correct tabs on the prototype
   card.  I have these two cards plugged into the ISA bus next to
   each other.

4) And finally, be careful when you do this -- make sure you have
   the correct tabs and pins indentified and make good solder
   connections.  And don't blame Hale Landis if you see smoke
   when you turn your system on!  And GOOD LUCK!


USING MW DMA MODE 0 WITH ATACT AND ATADEMO
------------------------------------------

To have ATACT or ATADEMO use ISA MW DM mode 0, use the DMA=ISAn
option on the ATACT or ATADEMO command line.  Your system will
require an ISA bus ATA host adapter with the ATA interface DMA
signals connected.


USING MW DMA MODES 1 OR 2
-------------------------

You need PCI bus ATA host adapter and the proper software to
program the host adapter hardware.  In ATADRVR, this support is
known as PCI Bus Mastering DMA support.  See below.


USING ULTRA DMA MODES 0, 1 OR 2
-------------------------------

You need a PCI bus ATA host adapter and the proper software to
program the host adapter hardware.  In ATADRVR, this support is
known as PCI Bus Mastering DMA support.  See below.


USING ULTRA DMA MODES 3 OR 4 OR 5
---------------------------------

You need a PCI bus ATA host adapter and the proper software to
program the host adapter hardware.  You *must* have an
80-conductor ATA cable to use these modes.  In ATADRVR, this
support is known as PCI Bus Mastering DMA support.  See below.


PCI BUS MASTERING DMA
---------------------

Most PCI bus motherboards now have two ATA host adapters built
into the "south bridge" chip of the motherboard chipset.  Most of
these motherboard chipsets will claim to be "Intel compatible"
and "SFF-8038 compatible".  It is difficult to determine how true
any of these claims may be since there is very little real
documentation on how these host adapters are setup and operated.

If the host adapter can be a PCI "bus master" then the host
adapter probably supports either (or both) ATA MW DMA or ATA
Ultra DMA.


SOME PROBLEMS WITH PCI BUS MASTERING DMA
----------------------------------------

You may want to read the SFF-8038 document and take note of the
description of the Interrupt (bit 2) and the BusMasterActive (bit
0) bits of the BMCR Status register.  These bits define four
states for the PCI DMA transfer:

   a) DMA transfer in progress,
   b) the device asserted INTRQ and the end of the PRD
      list was reached,
   c) the device asserted INTRQ and the end of the PRD
      list was not reached,
   d) the end of the PRD list was reached and the device
      has not asserted INTRQ.

States b) and c) indicate normal completion of a command.  State
d) will result in a timeout error when the host software doesn't
see the device complete the command (because the device is
waiting to transfer data with DMARQ asserted but the DMA channel
doesn't respond with DMACK and transfer any data).

When setting up DMA commands to an ATA device, or to an ATAPI
device when with a fixed sector size will be transferred, there
is no problem for the host software to program the DMA channel
for the exact number of bytes that will be transferred.  This
will result in state b) at the end of the command.

When setting up DMA commands to an ATAPI device for a command
that transfers an unknown number of bytes the host must program
the DMA channel to transfer a number of bytes that is more than
the maximum number of bytes the device is likely to transfer.
This will result in state c) at the end of the command.  The
problem with state c) is that there is no way to determine the
number of bytes the ATAPI device has transferred.  This makes
using PCI DMA with an ATAPI device highly questionable.

Note that most ATAPI Packet commands, even commands like Request
Sense or Inquiry, may transfer an different number of bytes each
time the command is executed.  Even if the "length" fields in the
data indicate there should be n bytes of data transferred, there
is no way to confirm that n bytes of data were actually
transferred.  So if you see data corruption problems with ATAPI
devices while using PCI DMA then this could be the problem.

It should be noted here that with ISA bus DMA controllers it is
possible to compute the number of bytes transferred by the
device.


USING ANY MW DMA MODES WITH ATACT OR ATADEMO
USING ANY ULTRA DMA MODES WITH ATACT OR ATADEMO
-----------------------------------------------------

To use any of these ATA DMA modes, your system must have an Intel
"south bridge" compatible PCI bus ATA host adapter.  Plus that
ATA host adapter must be SFF-8038 compatible.

To have ATACT or ATADEMO use PCI Bus Mastering DMA specify the
DMA=PCI option on the ATACT or ATADEMO command line.  This will
cause ATACT or ATADEMO to attempt PCI DMA configuration.  This
configuration requires the following:

1) More or more PCI bus mastering ATA host adapters must be
   found.  If the PCIDEV option is not specified and only one
   host adapter is found, PCIDEV will be defaulted to that one.
   If more than one host adapter is found the PCIDEV option must
   be specified to select the one that will be used.

2) The following data must exist in the PCI configuration data:

   a) offsets 10-17 or 18-1c may specify the I/O address of the
   primary or secondary ATA Command and Control block addresses.
   If these offsets are zero then it is assumed the host adapter
   is using the standard ATA host adapter addresses, either
   1Fx:3F6 with IRQ 14 or 17x:376 with IRQ 15.

   b) offsets 20-23 must specify an I/O address in the range
   0300H to FFF0H and the least significant 4 bits must be zero.
   This is the I/O address of the Bus Master Control Registers
   (BMCR).

3) The following data must exist in the BMCR:

   a) For testing of device 0 offset 2 bit 6 must be 1.

   b) For testing of device 1 offset 2 bit 5 must be 1.

4) The Identify Device data for the devices to be tested will be
   checked.  Identify Device words 63 and 88 must contain valid
   data indicating that the device is operating in a Multiword
   DMA or Ultra DMA mode.

Assuming your system passes all these requirements, then ATACT or
ATADEMO will be able to use PCI Bus Mastering DMA.


ADDITIONAL INFORMATION ABOUT PCI DMA
------------------------------------

Please note this additional information concerning PCI DMA:

1) At no time is the PCI configuration data for the ATA host
   adapter altered by ATADRVR, ATACT or ATADEMO.  The
   configuration data is where various PCI bus and ATA interface
   modes are configured and it is where the location of the BMCR
   registers is defined.  I hope you have documentation of this
   data for your host adapter and, if required, I hope you have a
   way to alter this data.  Maybe the system BIOS can affect
   changes to this data or maybe the vendor of your PCI chipset
   has supplied you with a utility program that can alter this
   data.

2) ATADRVR (also ATACT and ATADEMO) do not change the setting of
   bits 6 and 5 in offset 2 of the BMCR registers.  This offset
   is the BMCR.  These bits should be set to indicate if DMA is
   supported on devices 0 and 1. I hope your system BIOS is
   setting these bits correctly or, if required, you have a way
   to alter these bits.

3) You may not be able to determine which DMA mode is being used
   by the PCI ATA host adapter without using a logic analyzer to
   look at the ATA interface signals.  It appears that the PCI
   configuration data is unreliable on some host adapters (even
   when this data has Ultra DMA disabled, the host adapter uses
   Ultra DMA!).

4) You may experience complete and total system hangs requiring
   that the system be reset or powered off.  I have seen such
   hangs after 20+ hours of continuous running of ATACT and after
   ATACT has executed 200000+ Read/Write DMA commands with no
   errors.  Whatever is happening causes complete failure of the
   system including one system where the Reset button would not
   reset the system!


QUESTIONS OR PROBLEMS?
----------------------

Send your question(s) or problem description(s) to Hale Landis
via email at this address:

   [e-mail]

Visit Hale's web site:

   www.ata-atapi.com


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