lcd1602.syr

状态机的应用

FlipFlop datacnt_1 has been replicated 5 time(s)
FlipFlop datacnt_2 has been replicated 6 time(s)
FlipFlop datacnt_3 has been replicated 8 time(s)
FlipFlop datacnt_4 has been replicated 2 time(s)
FlipFlop datacnt_5 has been replicated 1 time(s)

Final Macro Processing ...

=========================================================================
Final Register Report

Macro Statistics
# Registers                                            : 66
 Flip-Flops                                            : 66

=========================================================================

=========================================================================
*                          Partition Report                             *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : LCD1602.ngr
Top Level Output File Name         : LCD1602
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 9

Cell Usage :
# BELS                             : 225
#      GND                         : 1
#      INV                         : 4
#      LUT1                        : 25
#      LUT2                        : 6
#      LUT2_D                      : 1
#      LUT2_L                      : 1
#      LUT3                        : 12
#      LUT3_L                      : 1
#      LUT4                        : 78
#      LUT4_D                      : 3
#      LUT4_L                      : 10
#      MUXCY                       : 31
#      MUXF5                       : 28
#      MUXF6                       : 1
#      VCC                         : 1
#      XORCY                       : 22
# FlipFlops/Latches                : 66
#      FDC                         : 5
#      FDE                         : 38
#      FDR                         : 23
# Clock Buffers                    : 2
#      BUFG                        : 1
#      BUFGP                       : 1
# IO Buffers                       : 8
#      IBUF                        : 1
#      OBUF                        : 7
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s500efg320-4 

 Number of Slices:                      82  out of   4656     1%  
 Number of Slice Flip Flops:            66  out of   9312     0%  
 Number of 4 input LUTs:               141  out of   9312     1%  
 Number of IOs:                          9
 Number of bonded IOBs:                  9  out of    232     3%  
 Number of GCLKs:                        2  out of     24     8%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
CLK                                | BUFGP                  | 24    |
LCD_Clk1                           | BUFG                   | 42    |
-----------------------------------+------------------------+-------+

Asynchronous Control Signals Information:
----------------------------------------
-----------------------------------+------------------------+-------+
Control Signal                     | Buffer(FF name)        | Load  |
-----------------------------------+------------------------+-------+
Reset_inv(Reset_inv1_INV_0:O)      | NONE(State_FFd1)       | 5     |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 6.836ns (Maximum Frequency: 146.284MHz)
   Minimum input arrival time before clock: 3.660ns
   Maximum output required time after clock: 4.740ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'CLK'
  Clock period: 6.654ns (frequency: 150.283MHz)
  Total number of paths / destination ports: 829 / 48
-------------------------------------------------------------------------
Delay:               6.654ns (Levels of Logic = 2)
  Source:            LCD_Clk (FF)
  Destination:       LCD_Clk (FF)
  Source Clock:      CLK rising
  Destination Clock: CLK rising

  Data Path: LCD_Clk to LCD_Clk
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE:C->Q              2   0.591   0.877  LCD_Clk (LCD_Clk1)
     BUFG:I->O            43   1.457   1.916  LCD_Clk_BUFG (LCD_Clk)
     INV:I->O              1   0.704   0.801  _not00031_INV_0 (_not0003)
     FDE:D                     0.308          LCD_Clk
    ----------------------------------------
    Total                      6.654ns (3.060ns logic, 3.594ns route)
                                       (46.0% logic, 54.0% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'LCD_Clk1'
  Clock period: 6.836ns (frequency: 146.284MHz)
  Total number of paths / destination ports: 1028 / 42
-------------------------------------------------------------------------
Delay:               6.836ns (Levels of Logic = 4)
  Source:            State_FFd3 (FF)
  Destination:       data_2 (FF)
  Source Clock:      LCD_Clk1 rising
  Destination Clock: LCD_Clk1 rising

  Data Path: State_FFd3 to data_2
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q             18   0.591   1.496  State_FFd3 (State_FFd3)
     LUT3:I1->O            2   0.704   0.956  State_Out41 (_cmp_eq0016)
     LUT4:I1->O            2   0.704   1.052  _mux0025<1>11_SW0 (N353)
     LUT4:I0->O            1   0.704   0.000  _mux0025<1>90_F (N367)
     MUXF5:I0->O           1   0.321   0.000  _mux0025<1>90 (_mux0025<1>)
     FDE:D                     0.308          data_2
    ----------------------------------------
    Total                      6.836ns (3.332ns logic, 3.504ns route)
                                       (48.7% logic, 51.3% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'LCD_Clk1'
  Total number of paths / destination ports: 37 / 37
-------------------------------------------------------------------------
Offset:              3.660ns (Levels of Logic = 1)
  Source:            Reset (PAD)
  Destination:       datacnt_0 (FF)
  Destination Clock: LCD_Clk1 rising

  Data Path: Reset to datacnt_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            38   1.218   1.887  Reset_IBUF (Reset_IBUF)
     FDE:CE                    0.555          data_3
    ----------------------------------------
    Total                      3.660ns (1.773ns logic, 1.887ns route)
                                       (48.4% logic, 51.6% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'CLK'
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset:              4.740ns (Levels of Logic = 1)
  Source:            LCD_Clk (FF)
  Destination:       LCD_EN (PAD)
  Source Clock:      CLK rising

  Data Path: LCD_Clk to LCD_EN
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE:C->Q              2   0.591   0.877  LCD_Clk (LCD_Clk1)
     OBUF:I->O                 3.272          LCD_EN_OBUF (LCD_EN)
    ----------------------------------------
    Total                      4.740ns (3.863ns logic, 0.877ns route)
                                       (81.5% logic, 18.5% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'LCD_Clk1'
  Total number of paths / destination ports: 5 / 5
-------------------------------------------------------------------------
Offset:              4.740ns (Levels of Logic = 1)
  Source:            LCD_RS (FF)
  Destination:       LCD_RS (PAD)
  Source Clock:      LCD_Clk1 rising

  Data Path: LCD_RS to LCD_RS
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              2   0.591   0.877  LCD_RS (LCD_RS_OBUF)
     OBUF:I->O                 3.272          LCD_RS_OBUF (LCD_RS)
    ----------------------------------------
    Total                      4.740ns (3.863ns logic, 0.877ns route)
                                       (81.5% logic, 18.5% route)

=========================================================================
CPU : 20.45 / 22.75 s | Elapsed : 21.00 / 23.00 s
 
--> 

Total memory usage is 154216 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    5 (   0 filtered)
Number of infos    :    7 (   0 filtered)