lcd1602.syr

状态机的应用

Release 8.2.03i - xst I.34
Copyright (c) 1995-2006 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to ./xst/projnav.tmp
CPU : 0.00 / 2.06 s | Elapsed : 0.00 / 2.00 s
 
--> Parameter xsthdpdir set to ./xst
CPU : 0.00 / 2.06 s | Elapsed : 0.00 / 2.00 s
 
--> Reading design: LCD1602.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) Design Hierarchy Analysis
  4) HDL Analysis
  5) HDL Synthesis
     5.1) HDL Synthesis Report
  6) Advanced HDL Synthesis
     6.1) Advanced HDL Synthesis Report
  7) Low Level Synthesis
  8) Partition Report
  9) Final Report
     9.1) Device utilization summary
     9.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "LCD1602.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "LCD1602"
Output Format                      : NGC
Target Device                      : xc3s500e-4-fg320

---- Source Options
Top Module Name                    : LCD1602
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
ROM Style                          : Auto
Mux Extraction                     : YES
Resource Sharing                   : YES
Multiplier Style                   : auto
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 500
Add Generic Clock Buffer(BUFG)     : 8
Register Duplication               : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto
Equivalent register Removal        : YES

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
RTL Output                         : Yes
Global Optimization                : AllClockNets
Write Timing Constraints           : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : LCD1602.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
safe_implementation                : No
Optimize Instantiated Primitives   : NO
use_clock_enable                   : Yes
use_sync_set                       : Yes
use_sync_reset                     : Yes

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
WARNING:HDLParsers:3300 - Invalid date.time ("I.34") scanned for file "C:/Xilinx/spartan" in dependency database.
WARNING:HDLParsers:11 - xst/work/hdpdeps.ref.3: Invalid unit type: 3E/jupiter/LCD/lcd.vhd
WARNING:HDLParsers:11 - xst/work/hdpdeps.ref.6: Invalid unit type: 3E/jupiter/LCD/lcd.vhd
WARNING:HDLParsers:3215 - Unit work/LCD1602 is now defined in a different file: was C:/Xilinx/spartan, now is C:/Xilinx/spartan 3E/jupiter/LCD/lcd.vhd
WARNING:HDLParsers:3215 - Unit work/LCD1602/Behavioral is now defined in a different file: was C:/Xilinx/spartan, now is C:/Xilinx/spartan 3E/jupiter/LCD/lcd.vhd
Compiling vhdl file "C:/Xilinx/spartan 3E/jupiter/LCD/lcd.vhd" in Library work.
Entity <lcd1602> compiled.
Entity <lcd1602> (Architecture <behavioral>) compiled.

=========================================================================
*                     Design Hierarchy Analysis                         *
=========================================================================
Analyzing hierarchy for entity <LCD1602> in library <work> (architecture <behavioral>).

Building hierarchy successfully finished.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <LCD1602> in library <work> (Architecture <behavioral>).
Entity <LCD1602> analyzed. Unit <LCD1602> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Performing bidirectional port resolution...

Synthesizing Unit <LCD1602>.
    Related source file is "C:/Xilinx/spartan 3E/jupiter/LCD/lcd.vhd".
    Found 40x8-bit ROM for signal <$rom0000> created at line 118.
    Found 40x8-bit ROM for signal <$rom0001> created at line 143.
    Found finite state machine <FSM_0> for signal <State>.
    -----------------------------------------------------------------------
    | States             | 7                                              |
    | Transitions        | 20                                             |
    | Inputs             | 12                                             |
    | Outputs            | 7                                              |
    | Clock              | LCD_Clk (rising_edge)                          |
    | Reset              | Reset (negative)                               |
    | Reset type         | asynchronous                                   |
    | Reset State        | write_instr                                    |
    | Power Up State     | write_instr                                    |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 16x10-bit ROM for signal <$rom0002>.
    Found 1-bit register for signal <LCD_RS>.
    Found 4-bit register for signal <data>.
    Found 6-bit adder for signal <$addsub0000>.
    Found 23-bit comparator less for signal <$cmp_lt0000> created at line 59.
    Found 6-bit register for signal <datacnt>.
    Found 1-bit register for signal <LCD_Clk>.
    Found 23-bit up counter for signal <n1>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred   3 ROM(s).
	inferred   1 Counter(s).
	inferred  12 D-type flip-flop(s).
	inferred   1 Adder/Subtractor(s).
	inferred   1 Comparator(s).
Unit <LCD1602> synthesized.

INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.

=========================================================================
HDL Synthesis Report

Macro Statistics
# ROMs                                                 : 3
 16x10-bit ROM                                         : 1
 40x8-bit ROM                                          : 2
# Adders/Subtractors                                   : 1
 6-bit adder                                           : 1
# Counters                                             : 1
 23-bit up counter                                     : 1
# Registers                                            : 4
 1-bit register                                        : 2
 4-bit register                                        : 1
 6-bit register                                        : 1
# Comparators                                          : 1
 23-bit comparator less                                : 1

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <State> on signal <State[1:3]> with gray encoding.
-------------------------------
 State             | Encoding
-------------------------------
 write_instr       | 000
 write_dataup4_1   | 001
 write_datadown4_1 | 011
 set_ddramaddup    | 010
 set_ddramadddown  | 110
 write_dataup4_2   | 111
 write_datadown4_2 | 101
-------------------------------
Loading device for application Rf_Device from file '3s500e.nph' in environment C:\Xilinx.
INFO:Xst:1651 - Address input of ROM <Mrom__rom0001> is tied to register <datacnt>.
INFO:Xst:2504 - HDL ADVISOR - Initial contents of this register prevents it from being combined with the ROM for implementation as read-only block RAM.
INFO:Xst:1651 - Address input of ROM <Mrom__rom0000> is tied to register <datacnt>.
INFO:Xst:2504 - HDL ADVISOR - Initial contents of this register prevents it from being combined with the ROM for implementation as read-only block RAM.
INFO:Xst:1651 - Address input of ROM <Mrom__rom0002> is tied to register <datacnt>.
INFO:Xst:2504 - HDL ADVISOR - Initial contents of this register prevents it from being combined with the ROM for implementation as read-only block RAM.

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# FSMs                                                 : 1
# ROMs                                                 : 3
 16x10-bit ROM                                         : 1
 40x8-bit ROM                                          : 2
# Adders/Subtractors                                   : 1
 6-bit adder                                           : 1
# Counters                                             : 1
 23-bit up counter                                     : 1
# Registers                                            : 15
 Flip-Flops                                            : 15
# Comparators                                          : 1
 23-bit comparator less                                : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <LCD1602> ...

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block LCD1602, actual ratio is 1.
FlipFlop State_FFd1 has been replicated 1 time(s)
FlipFlop datacnt_0 has been replicated 5 time(s)