lcd1602.twr

状态机的应用

--------------------------------------------------------------------------------
Release 8.2.03i Trace 
Copyright (c) 1995-2006 Xilinx, Inc.  All rights reserved.

C:\Xilinx\bin\nt\trce.exe -ise C:/Xilinx/spartan 3E/jupiter/LCD/LCD.ise
-intstyle ise -e 3 -l 3 -s 4 -xml LCD1602 LCD1602.ncd -o LCD1602.twr
LCD1602.pcf -ucf LCD1602.ucf

Design file:              lcd1602.ncd
Physical constraint file: lcd1602.pcf
Device,speed:             xc3s500e,-4 (PRODUCTION 1.26 2006-08-18)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
--------------------------------------------------------------------------------

INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths 
   option. All paths that are not constrained will be reported in the 
   unconstrained paths section(s) of the report.



Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Clock CLK to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  | Clock  |
Destination |   to PAD   |Internal Clock(s) | Phase  |
------------+------------+------------------+--------+
LCD_EN      |   15.033(R)|CLK_BUFGP         |   0.000|
------------+------------+------------------+--------+

Clock to Setup on destination clock CLK
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
CLK            |    4.614|         |         |         |
---------------+---------+---------+---------+---------+


Analysis completed Fri Sep 21 09:17:31 2007
--------------------------------------------------------------------------------

Trace Settings:
-------------------------
Trace Settings 

Peak Memory Usage: 129 MB