tft.tan.qmsg

stm32数码相框

{ "Info" "ITDB_FULL_TCO_RESULT" "clkin YSYNC lcd:inst\|YSYNC 20.088 ns register " "Info: tco from clock \"clkin\" to destination pin \"YSYNC\" through register \"lcd:inst\|YSYNC\" is 20.088 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkin source 14.691 ns + Longest register " "Info: + Longest clock path from clock \"clkin\" to source register is 14.691 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clkin 1 CLK PIN_20 170 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_20; Fanout = 170; CLK Node = 'clkin'" {  } { { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { clkin } "NODE_NAME" } } { "TFT.bdf" "" { Schematic "F:/570/570_h_speed/TFT.bdf" { { 128 -192 -24 144 "clkin" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(1.294 ns) 4.057 ns lcd:inst\|CLKOUT 2 REG LC_X12_Y4_N8 16 " "Info: 2: + IC(1.600 ns) + CELL(1.294 ns) = 4.057 ns; Loc. = LC_X12_Y4_N8; Fanout = 16; REG Node = 'lcd:inst\|CLKOUT'" {  } { { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "2.894 ns" { clkin lcd:inst|CLKOUT } "NODE_NAME" } } { "lcd.v" "" { Text "F:/570/570_h_speed/lcd.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(4.210 ns) + CELL(1.294 ns) 9.561 ns lcd:inst\|HSYNC 3 REG LC_X8_Y4_N5 18 " "Info: 3: + IC(4.210 ns) + CELL(1.294 ns) = 9.561 ns; Loc. = LC_X8_Y4_N5; Fanout = 18; REG Node = 'lcd:inst\|HSYNC'" {  } { { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "5.504 ns" { lcd:inst|CLKOUT lcd:inst|HSYNC } "NODE_NAME" } } { "lcd.v" "" { Text "F:/570/570_h_speed/lcd.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(4.212 ns) + CELL(0.918 ns) 14.691 ns lcd:inst\|YSYNC 4 REG LC_X6_Y4_N6 2 " "Info: 4: + IC(4.212 ns) + CELL(0.918 ns) = 14.691 ns; Loc. = LC_X6_Y4_N6; Fanout = 2; REG Node = 'lcd:inst\|YSYNC'" {  } { { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "5.130 ns" { lcd:inst|HSYNC lcd:inst|YSYNC } "NODE_NAME" } } { "lcd.v" "" { Text "F:/570/570_h_speed/lcd.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.669 ns ( 31.78 % ) " "Info: Total cell delay = 4.669 ns ( 31.78 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "10.022 ns ( 68.22 % ) " "Info: Total interconnect delay = 10.022 ns ( 68.22 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "14.691 ns" { clkin lcd:inst|CLKOUT lcd:inst|HSYNC lcd:inst|YSYNC } "NODE_NAME" } } { "c:/electron/altera/91/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/electron/altera/91/quartus/bin/Technology_Viewer.qrui" "14.691 ns" { clkin {} clkin~combout {} lcd:inst|CLKOUT {} lcd:inst|HSYNC {} lcd:inst|YSYNC {} } { 0.000ns 0.000ns 1.600ns 4.210ns 4.212ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "lcd.v" "" { Text "F:/570/570_h_speed/lcd.v" 5 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.021 ns + Longest register pin " "Info: + Longest register to pin delay is 5.021 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lcd:inst\|YSYNC 1 REG LC_X6_Y4_N6 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X6_Y4_N6; Fanout = 2; REG Node = 'lcd:inst\|YSYNC'" {  } { { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { lcd:inst|YSYNC } "NODE_NAME" } } { "lcd.v" "" { Text "F:/570/570_h_speed/lcd.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.699 ns) + CELL(2.322 ns) 5.021 ns YSYNC 2 PIN PIN_70 0 " "Info: 2: + IC(2.699 ns) + CELL(2.322 ns) = 5.021 ns; Loc. = PIN_70; Fanout = 0; PIN Node = 'YSYNC'" {  } { { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "5.021 ns" { lcd:inst|YSYNC YSYNC } "NODE_NAME" } } { "TFT.bdf" "" { Schematic "F:/570/570_h_speed/TFT.bdf" { { 256 320 496 272 "YSYNC" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.322 ns ( 46.25 % ) " "Info: Total cell delay = 2.322 ns ( 46.25 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "2.699 ns ( 53.75 % ) " "Info: Total interconnect delay = 2.699 ns ( 53.75 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "5.021 ns" { lcd:inst|YSYNC YSYNC } "NODE_NAME" } } { "c:/electron/altera/91/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/electron/altera/91/quartus/bin/Technology_Viewer.qrui" "5.021 ns" { lcd:inst|YSYNC {} YSYNC {} } { 0.000ns 2.699ns } { 0.000ns 2.322ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1}  } { { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "14.691 ns" { clkin lcd:inst|CLKOUT lcd:inst|HSYNC lcd:inst|YSYNC } "NODE_NAME" } } { "c:/electron/altera/91/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/electron/altera/91/quartus/bin/Technology_Viewer.qrui" "14.691 ns" { clkin {} clkin~combout {} lcd:inst|CLKOUT {} lcd:inst|HSYNC {} lcd:inst|YSYNC {} } { 0.000ns 0.000ns 1.600ns 4.210ns 4.212ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.918ns } "" } } { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "5.021 ns" { lcd:inst|YSYNC YSYNC } "NODE_NAME" } } { "c:/electron/altera/91/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/electron/altera/91/quartus/bin/Technology_Viewer.qrui" "5.021 ns" { lcd:inst|YSYNC {} YSYNC {} } { 0.000ns 2.699ns } { 0.000ns 2.322ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 -1}
{ "Info" "ITDB_TH_RESULT" "lcd:inst\|DATA\[14\] sram_data\[14\] clkin -1.112 ns register " "Info: th for register \"lcd:inst\|DATA\[14\]\" (data pin = \"sram_data\[14\]\", clock pin = \"clkin\") is -1.112 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkin destination 3.681 ns + Longest register " "Info: + Longest clock path from clock \"clkin\" to destination register is 3.681 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clkin 1 CLK PIN_20 170 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_20; Fanout = 170; CLK Node = 'clkin'" {  } { { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { clkin } "NODE_NAME" } } { "TFT.bdf" "" { Schematic "F:/570/570_h_speed/TFT.bdf" { { 128 -192 -24 144 "clkin" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(0.918 ns) 3.681 ns lcd:inst\|DATA\[14\] 2 REG LC_X11_Y6_N4 1 " "Info: 2: + IC(1.600 ns) + CELL(0.918 ns) = 3.681 ns; Loc. = LC_X11_Y6_N4; Fanout = 1; REG Node = 'lcd:inst\|DATA\[14\]'" {  } { { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "2.518 ns" { clkin lcd:inst|DATA[14] } "NODE_NAME" } } { "lcd.v" "" { Text "F:/570/570_h_speed/lcd.v" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 56.53 % ) " "Info: Total cell delay = 2.081 ns ( 56.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.600 ns ( 43.47 % ) " "Info: Total interconnect delay = 1.600 ns ( 43.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "3.681 ns" { clkin lcd:inst|DATA[14] } "NODE_NAME" } } { "c:/electron/altera/91/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/electron/altera/91/quartus/bin/Technology_Viewer.qrui" "3.681 ns" { clkin {} clkin~combout {} lcd:inst|DATA[14] {} } { 0.000ns 0.000ns 1.600ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TH_DELAY" "0.221 ns + " "Info: + Micro hold delay of destination is 0.221 ns" {  } { { "lcd.v" "" { Text "F:/570/570_h_speed/lcd.v" 117 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.014 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.014 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sram_data\[14\] 1 PIN PIN_112 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_112; Fanout = 1; PIN Node = 'sram_data\[14\]'" {  } { { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "" { sram_data[14] } "NODE_NAME" } } { "TFT.bdf" "" { Schematic "F:/570/570_h_speed/TFT.bdf" { { 96 320 498 112 "sram_data\[15..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns sram_data~1 2 COMB IOC_X11_Y8_N1 1 " "Info: 2: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = IOC_X11_Y8_N1; Fanout = 1; COMB Node = 'sram_data~1'" {  } { { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "1.132 ns" { sram_data[14] sram_data~1 } "NODE_NAME" } } { "TFT.bdf" "" { Schematic "F:/570/570_h_speed/TFT.bdf" { { 96 320 498 112 "sram_data\[15..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.821 ns) + CELL(1.061 ns) 5.014 ns lcd:inst\|DATA\[14\] 3 REG LC_X11_Y6_N4 1 " "Info: 3: + IC(2.821 ns) + CELL(1.061 ns) = 5.014 ns; Loc. = LC_X11_Y6_N4; Fanout = 1; REG Node = 'lcd:inst\|DATA\[14\]'" {  } { { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "3.882 ns" { sram_data~1 lcd:inst|DATA[14] } "NODE_NAME" } } { "lcd.v" "" { Text "F:/570/570_h_speed/lcd.v" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.193 ns ( 43.74 % ) " "Info: Total cell delay = 2.193 ns ( 43.74 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "2.821 ns ( 56.26 % ) " "Info: Total interconnect delay = 2.821 ns ( 56.26 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "5.014 ns" { sram_data[14] sram_data~1 lcd:inst|DATA[14] } "NODE_NAME" } } { "c:/electron/altera/91/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/electron/altera/91/quartus/bin/Technology_Viewer.qrui" "5.014 ns" { sram_data[14] {} sram_data~1 {} lcd:inst|DATA[14] {} } { 0.000ns 0.000ns 2.821ns } { 0.000ns 1.132ns 1.061ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1}  } { { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "3.681 ns" { clkin lcd:inst|DATA[14] } "NODE_NAME" } } { "c:/electron/altera/91/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/electron/altera/91/quartus/bin/Technology_Viewer.qrui" "3.681 ns" { clkin {} clkin~combout {} lcd:inst|DATA[14] {} } { 0.000ns 0.000ns 1.600ns } { 0.000ns 1.163ns 0.918ns } "" } } { "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/electron/altera/91/quartus/bin/TimingClosureFloorplan.fld" "" "5.014 ns" { sram_data[14] sram_data~1 lcd:inst|DATA[14] } "NODE_NAME" } } { "c:/electron/altera/91/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/electron/altera/91/quartus/bin/Technology_Viewer.qrui" "5.014 ns" { sram_data[14] {} sram_data~1 {} lcd:inst|DATA[14] {} } { 0.000ns 0.000ns 2.821ns } { 0.000ns 1.132ns 1.061ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 3 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "130 " "Info: Peak virtual memory: 130 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Wed Jan 12 20:45:54 2011 " "Info: Processing ended: Wed Jan 12 20:45:54 2011" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Info: Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}