📄 seg7_dsp.rpt
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# Q21
# Q24
# !Q23;
-- Node name is ':504'
-- Equation name is '_LC5_B18', type is buried
!_LC5_B18 = _LC5_B18~NOT;
_LC5_B18~NOT = LCELL( _EQ044);
_EQ044 = Q22
# !Q21
# Q24
# !Q23;
-- Node name is ':509'
-- Equation name is '_LC6_B18', type is buried
_LC6_B18 = LCELL( _EQ045);
_EQ045 = !Q21 & Q22 & Q23 & !Q24;
-- Node name is ':514'
-- Equation name is '_LC1_B19', type is buried
!_LC1_B19 = _LC1_B19~NOT;
_LC1_B19~NOT = LCELL( _EQ046);
_EQ046 = !Q22
# !Q21
# Q24
# !Q23;
-- Node name is '~519~1'
-- Equation name is '~519~1', location is LC2_B21, type is buried.
-- synthesized logic cell
_LC2_B21 = LCELL( _EQ047);
_EQ047 = !Q23 & Q24;
-- Node name is ':519'
-- Equation name is '_LC1_B18', type is buried
_LC1_B18 = LCELL( _EQ048);
_EQ048 = _LC2_B21 & !Q21 & !Q22;
-- Node name is ':524'
-- Equation name is '_LC5_B24', type is buried
!_LC5_B24 = _LC5_B24~NOT;
_LC5_B24~NOT = LCELL( _EQ049);
_EQ049 = Q22
# !Q21
# !_LC2_B21;
-- Node name is ':529'
-- Equation name is '_LC2_B24', type is buried
_LC2_B24 = LCELL( _EQ050);
_EQ050 = _LC2_B21 & !Q21 & Q22;
-- Node name is ':554'
-- Equation name is '_LC3_B24', type is buried
_LC3_B24 = LCELL( _EQ051);
_EQ051 = Q21 & Q22 & Q23 & Q24;
-- Node name is ':660'
-- Equation name is '_LC6_C21', type is buried
_LC6_C21 = LCELL( _EQ052);
_EQ052 = Q22 & Q24
# Q22 & !Q23
# !Q21 & Q22
# !Q23 & Q24
# Q21 & Q24
# !Q21 & Q23 & !Q24
# Q21 & !Q22 & Q23;
-- Node name is ':685'
-- Equation name is '_LC1_B17', type is buried
_LC1_B17 = LCELL( _EQ053);
_EQ053 = _LC2_B21
# _LC2_B17;
-- Node name is ':697'
-- Equation name is '_LC5_B17', type is buried
_LC5_B17 = LCELL( _EQ054);
_EQ054 = _LC3_B17
# _LC2_B22
# _LC1_B17 & !_LC1_B19;
-- Node name is ':709'
-- Equation name is '_LC5_C19', type is buried
_LC5_C19 = LCELL( _EQ055);
_EQ055 = !_LC1_C4 & !_LC1_C19 & _LC5_B17
# _LC2_C19;
-- Node name is ':738'
-- Equation name is '_LC1_B24', type is buried
_LC1_B24 = LCELL( _EQ056);
_EQ056 = _LC2_B24 & !_LC5_B24
# _LC3_B24 & !_LC5_B24
# _LC4_B24 & !_LC5_B24;
-- Node name is ':742'
-- Equation name is '_LC2_B18', type is buried
_LC2_B18 = LCELL( _EQ057);
_EQ057 = _LC6_B18
# _LC1_B18 & !_LC1_B19
# !_LC1_B19 & _LC1_B24;
-- Node name is ':756'
-- Equation name is '_LC4_B18', type is buried
_LC4_B18 = LCELL( _EQ058);
_EQ058 = _LC2_B18 & !_LC2_B22 & !_LC3_B18 & !_LC5_B18;
-- Node name is ':760'
-- Equation name is '_LC4_C19', type is buried
_LC4_C19 = LCELL( _EQ059);
_EQ059 = _LC2_C19
# !_LC1_C19 & _LC2_C3
# !_LC1_C19 & _LC4_B18;
-- Node name is ':778'
-- Equation name is '_LC4_B24', type is buried
_LC4_B24 = LCELL( _EQ060);
_EQ060 = Q21 & Q22 & !Q23 & Q24
# !Q21 & Q23 & Q24
# !Q22 & Q23 & Q24;
-- Node name is ':811'
-- Equation name is '_LC2_C20', type is buried
_LC2_C20 = LCELL( _EQ061);
_EQ061 = Q22 & !Q23 & !Q24
# !Q21 & !Q23 & !Q24
# !Q21 & Q22 & !Q24
# !Q21 & !Q22 & !Q23
# !Q22 & !Q23 & Q24
# Q21 & Q22 & !Q23
# Q21 & !Q22 & Q23
# !Q21 & Q22 & Q23
# !Q21 & !Q22 & Q24;
-- Node name is ':862'
-- Equation name is '_LC1_C24', type is buried
_LC1_C24 = LCELL( _EQ062);
_EQ062 = !Q22 & !Q24
# Q23 & !Q24
# Q21 & !Q22
# !Q23 & Q24
# !Q22 & !Q23
# Q21 & !Q23
# Q21 & !Q24;
-- Node name is ':913'
-- Equation name is '_LC1_C22', type is buried
_LC1_C22 = LCELL( _EQ063);
_EQ063 = !Q21 & !Q22 & !Q24
# !Q23 & !Q24
# Q21 & !Q22 & Q24
# !Q21 & !Q23
# !Q22 & !Q23
# Q21 & Q22 & !Q24;
-- Node name is ':928'
-- Equation name is '_LC2_B17', type is buried
_LC2_B17 = LCELL( _EQ064);
_EQ064 = !Q21 & Q23 & Q24
# Q22 & Q23 & Q24;
-- Node name is '~949~1'
-- Equation name is '~949~1', location is LC3_B17, type is buried.
-- synthesized logic cell
_LC3_B17 = LCELL( _EQ065);
_EQ065 = Q21 & !Q22 & Q23 & !Q24
# !Q21 & Q22 & Q23 & !Q24;
-- Node name is '~958~1'
-- Equation name is '~958~1', location is LC1_C4, type is buried.
-- synthesized logic cell
!_LC1_C4 = _LC1_C4~NOT;
_LC1_C4~NOT = LCELL( _EQ066);
_EQ066 = !Q22
# Q24
# Q23;
-- Node name is ':964'
-- Equation name is '_LC6_B20', type is buried
_LC6_B20 = LCELL( _EQ067);
_EQ067 = Q21 & Q23 & !Q24
# !Q21 & !Q23
# !Q22 & !Q23 & Q24
# Q22 & !Q24
# !Q21 & Q24
# !Q21 & Q22
# Q22 & Q23;
Project Information d:\lu\vhdl-digitallogic\disk\ch7\seg7_dsp.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = on
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = on
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:01
Partitioner 00:00:00
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:04
Memory Allocated
-----------------
Peak memory allocated during compilation = 9,370K
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