📄 seg7_dsp.rpt
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@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: d:\lu\vhdl-digitallogic\disk\ch7\seg7_dsp.rpt
seg7_dspa
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
81 - - C -- OUTPUT 0 1 0 0 NUMOUT0
83 - - C -- OUTPUT 0 1 0 0 NUMOUT1
79 - - C -- OUTPUT 0 1 0 0 NUMOUT2
82 - - C -- OUTPUT 0 1 0 0 NUMOUT3
23 - - B -- OUTPUT 0 1 0 0 SEGOUT0
26 - - C -- OUTPUT 0 1 0 0 SEGOUT1
27 - - C -- OUTPUT 0 1 0 0 SEGOUT2
28 - - C -- OUTPUT 0 1 0 0 SEGOUT3
29 - - C -- OUTPUT 0 1 0 0 SEGOUT4
30 - - C -- OUTPUT 0 1 0 0 SEGOUT5
31 - - C -- OUTPUT 0 1 0 0 SEGOUT6
32 - - C -- OUTPUT 0 0 0 0 SEGOUT7
33 - - C -- OUTPUT 0 1 0 0 SELOUT0
36 - - - 24 OUTPUT 0 1 0 0 SELOUT1
37 - - - 23 OUTPUT 0 1 0 0 SELOUT2
80 - - C -- OUTPUT 0 1 0 0 SELOUT3
78 - - C -- OUTPUT 0 1 0 0 SELOUT4
128 - - - 13 OUTPUT 0 1 0 0 SELOUT5
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\lu\vhdl-digitallogic\disk\ch7\seg7_dsp.rpt
seg7_dspa
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 2 - A 22 AND2 0 3 0 3 |LPM_ADD_SUB:156|addcore:adder|:143
- 1 - A 22 AND2 0 3 0 4 |LPM_ADD_SUB:156|addcore:adder|:151
- 1 - A 21 AND2 0 4 0 4 |LPM_ADD_SUB:156|addcore:adder|:163
- 7 - A 13 AND2 0 4 0 4 |LPM_ADD_SUB:156|addcore:adder|:175
- 2 - A 13 AND2 0 4 0 3 |LPM_ADD_SUB:156|addcore:adder|:187
- 1 - C 17 AND2 0 3 0 4 |LPM_ADD_SUB:156|addcore:adder|:195
- 1 - C 02 AND2 0 4 0 4 |LPM_ADD_SUB:156|addcore:adder|:207
- 4 - C 01 AND2 0 4 0 3 |LPM_ADD_SUB:156|addcore:adder|:219
- 2 - C 01 DFFE + 0 3 1 19 Q24 (:53)
- 5 - C 01 DFFE + 0 2 1 20 Q23 (:54)
- 1 - C 01 DFFE + 0 1 1 23 Q22 (:55)
- 3 - C 01 DFFE + 0 3 1 21 Q21 (:56)
- 6 - C 01 DFFE + 0 2 0 2 Q20 (:57)
- 7 - C 01 DFFE + 0 1 0 3 Q19 (:58)
- 4 - C 02 DFFE + 0 3 0 1 Q18 (:59)
- 3 - C 02 DFFE + 0 2 0 2 Q17 (:60)
- 2 - C 02 DFFE + 0 1 0 3 Q16 (:61)
- 2 - C 18 DFFE + 0 2 0 7 Q15 (:62)
- 1 - C 13 DFFE + 0 1 0 8 Q14 (:63)
- 1 - A 13 DFFE + 0 3 0 7 Q13 (:64)
- 3 - A 13 DFFE + 0 2 0 2 Q12 (:65)
- 6 - A 13 DFFE + 0 1 0 3 Q11 (:66)
- 5 - A 13 DFFE + 0 3 0 1 Q10 (:67)
- 4 - A 13 DFFE + 0 2 0 2 Q9 (:68)
- 8 - A 13 DFFE + 0 1 0 3 Q8 (:69)
- 2 - A 21 DFFE + 0 3 0 1 Q7 (:70)
- 3 - A 21 DFFE + 0 2 0 2 Q6 (:71)
- 4 - A 21 DFFE + 0 1 0 3 Q5 (:72)
- 7 - A 22 DFFE + 0 2 0 1 Q4 (:73)
- 6 - A 22 DFFE + 0 1 0 2 Q3 (:74)
- 5 - A 22 DFFE + 0 2 0 1 Q2 (:75)
- 4 - A 22 DFFE + 0 1 0 2 Q1 (:76)
- 3 - A 22 DFFE + 0 0 0 3 Q0 (:77)
- 8 - C 23 OR2 ! 0 3 1 0 :292
- 1 - C 23 OR2 ! 0 3 1 0 :296
- 3 - C 23 OR2 ! 0 3 1 0 :300
- 3 - C 16 OR2 ! 0 3 1 0 :304
- 7 - C 15 OR2 ! 0 3 1 0 :308
- 1 - C 14 OR2 ! 0 3 1 0 :312
- 2 - C 19 AND2 0 4 0 2 :479
- 1 - C 19 OR2 ! 0 4 0 2 :484
- 2 - C 03 AND2 0 4 0 1 :489
- 3 - B 18 OR2 ! 0 4 0 1 :494
- 2 - B 22 OR2 ! 0 4 0 2 :499
- 5 - B 18 OR2 ! 0 4 0 1 :504
- 6 - B 18 AND2 0 4 0 1 :509
- 1 - B 19 OR2 ! 0 4 0 2 :514
- 2 - B 21 AND2 s 0 2 0 4 ~519~1
- 1 - B 18 AND2 0 3 0 1 :519
- 5 - B 24 OR2 ! 0 3 0 1 :524
- 2 - B 24 AND2 0 3 0 1 :529
- 3 - B 24 AND2 0 4 0 1 :554
- 6 - C 21 OR2 0 4 1 0 :660
- 1 - B 17 OR2 0 2 0 1 :685
- 5 - B 17 OR2 0 4 0 1 :697
- 5 - C 19 OR2 0 4 1 0 :709
- 1 - B 24 OR2 0 4 0 1 :738
- 2 - B 18 OR2 0 4 0 1 :742
- 4 - B 18 AND2 0 4 0 1 :756
- 4 - C 19 OR2 0 4 1 0 :760
- 4 - B 24 OR2 0 4 0 1 :778
- 2 - C 20 OR2 0 4 1 0 :811
- 1 - C 24 OR2 0 4 1 0 :862
- 1 - C 22 OR2 0 4 1 0 :913
- 2 - B 17 OR2 0 4 0 1 :928
- 3 - B 17 OR2 s 0 4 0 1 ~949~1
- 1 - C 04 OR2 s ! 0 3 0 1 ~958~1
- 6 - B 20 OR2 0 4 1 0 :964
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\lu\vhdl-digitallogic\disk\ch7\seg7_dsp.rpt
seg7_dspa
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 2/ 48( 4%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 4/ 96( 4%) 0/ 48( 0%) 5/ 48( 10%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
C: 9/ 96( 9%) 1/ 48( 2%) 13/ 48( 27%) 0/16( 0%) 14/16( 87%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 4/24( 16%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
14: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
24: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\lu\vhdl-digitallogic\disk\ch7\seg7_dsp.rpt
seg7_dspa
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 25 CP
Device-Specific Information: d:\lu\vhdl-digitallogic\disk\ch7\seg7_dsp.rpt
seg7_dspa
** EQUATIONS **
CP : INPUT;
-- Node name is 'NUMOUT0'
-- Equation name is 'NUMOUT0', type is output
NUMOUT0 = Q21;
-- Node name is 'NUMOUT1'
-- Equation name is 'NUMOUT1', type is output
NUMOUT1 = Q22;
-- Node name is 'NUMOUT2'
-- Equation name is 'NUMOUT2', type is output
NUMOUT2 = Q23;
-- Node name is 'NUMOUT3'
-- Equation name is 'NUMOUT3', type is output
NUMOUT3 = Q24;
-- Node name is ':77' = 'Q0'
-- Equation name is 'Q0', location is LC3_A22, type is buried.
Q0 = DFFE(!Q0, GLOBAL( CP), VCC, VCC, VCC);
-- Node name is ':76' = 'Q1'
-- Equation name is 'Q1', location is LC4_A22, type is buried.
Q1 = DFFE( _EQ001, GLOBAL( CP), VCC, VCC, VCC);
_EQ001 = Q0 & !Q1
# !Q0 & Q1;
-- Node name is ':75' = 'Q2'
-- Equation name is 'Q2', location is LC5_A22, type is buried.
Q2 = DFFE( _EQ002, GLOBAL( CP), VCC, VCC, VCC);
_EQ002 = !Q0 & Q2
# !Q1 & Q2
# Q0 & Q1 & !Q2;
-- Node name is ':74' = 'Q3'
-- Equation name is 'Q3', location is LC6_A22, type is buried.
Q3 = DFFE( _EQ003, GLOBAL( CP), VCC, VCC, VCC);
_EQ003 = !_LC2_A22 & Q3
# _LC2_A22 & !Q3;
-- Node name is ':73' = 'Q4'
-- Equation name is 'Q4', location is LC7_A22, type is buried.
Q4 = DFFE( _EQ004, GLOBAL( CP), VCC, VCC, VCC);
_EQ004 = !Q3 & Q4
# !_LC2_A22 & Q4
# _LC2_A22 & Q3 & !Q4;
-- Node name is ':72' = 'Q5'
-- Equation name is 'Q5', location is LC4_A21, type is buried.
Q5 = DFFE( _EQ005, GLOBAL( CP), VCC, VCC, VCC);
_EQ005 = !_LC1_A22 & Q5
# _LC1_A22 & !Q5;
-- Node name is ':71' = 'Q6'
-- Equation name is 'Q6', location is LC3_A21, type is buried.
Q6 = DFFE( _EQ006, GLOBAL( CP), VCC, VCC, VCC);
_EQ006 = !Q5 & Q6
# !_LC1_A22 & Q6
# _LC1_A22 & Q5 & !Q6;
-- Node name is ':70' = 'Q7'
-- Equation name is 'Q7', location is LC2_A21, type is buried.
Q7 = DFFE( _EQ007, GLOBAL( CP), VCC, VCC, VCC);
_EQ007 = !Q5 & Q7
# !_LC1_A22 & Q7
# !Q6 & Q7
# _LC1_A22 & Q5 & Q6 & !Q7;
-- Node name is ':69' = 'Q8'
-- Equation name is 'Q8', location is LC8_A13, type is buried.
Q8 = DFFE( _EQ008, GLOBAL( CP), VCC, VCC, VCC);
_EQ008 = !_LC1_A21 & Q8
# _LC1_A21 & !Q8;
-- Node name is ':68' = 'Q9'
-- Equation name is 'Q9', location is LC4_A13, type is buried.
Q9 = DFFE( _EQ009, GLOBAL( CP), VCC, VCC, VCC);
_EQ009 = !Q8 & Q9
# !_LC1_A21 & Q9
# _LC1_A21 & Q8 & !Q9;
-- Node name is ':67' = 'Q10'
-- Equation name is 'Q10', location is LC5_A13, type is buried.
Q10 = DFFE( _EQ010, GLOBAL( CP), VCC, VCC, VCC);
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