debunce.vhd

有用的VHDL源代码

--*************************************************************
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

--**************************************************************
ENTITY Debunce is
	PORT(
		 CP			: IN    STD_LOGIC;				-- CLOCK
		 Key	    : IN    STD_LOGIC;				-- Input Signal
		 DLY_OUT    : OUT   STD_LOGIC; 				-- Debounce O/P
		 DIF_OUT	: OUT   STD_LOGIC				-- Differential O/P
		);
END Debunce;

--**************************************************************
ARCHITECTURE a OF Debunce IS
	SIGNAL SAMPLE, DLY, NDLY, DIFF	: STD_LOGIC;	-- Binary 
BEGIN

Free_Counter : Block		-- 计数器  & 产生扫描信号             	
 	Signal 	Q	: STD_LOGIC_VECTOR(14 DOWNTO 0);
	Signal  D0 : STD_LOGIC;
Begin
	
	PROCESS (CP)					-- 计数器计数       
	Begin
		IF CP'Event AND CP='1' then
			D0 <= Q(14);
			Q <= Q+1;			
		END IF;
	END PROCESS;
	
	SAMPLE <= Q(14) AND NOT D0;		--产生125HZ脉冲?    
	--SAMPLE <= Q(1) AND NOT D0;	
END Block Free_Counter;											


Debunce : Block							-- Debounce
	SIGNAL D0, D1, S, R : STD_LOGIC;  
Begin
	Process (CP)
	Begin
		IF CP'EVENT AND CP='1' THEN
			IF SAMPLE = '1' THEN
				D1 <= D0; D0 <= KEY;		-- Two Stage Delay
				S <= D0 AND D1;				-- Generate S、R	
				R <= NOT D0 AND NOT D1;
			END IF;		
		END IF;
	End Process;	
	DLY <= R NOR NDLY;			-- Debounce O/P
	NDLY <=S NOR DLY;	
	DLY_OUT <= DLY;

End Block Debunce;


Differential : Block				--	Differential
	Signal D1,D0 : STD_LOGIC;
BEGIN
	Process (CP)
	Begin
		IF CP'EVENT AND CP='1' THEN
			D1 <= D0; D0 <= DLY;	-- Two State Delay
		END IF;
	End Process;	
	DIFF <= D0 AND NOT D1;			-- Differential
END Block Differential;

DIF_OUT <= DIFF;					-- Differential O/P

END a;