📄 timer_dsp.rpt
字号:
- 4 - C 16 OR2 ! 0 2 0 1 :714
- 2 - C 16 OR2 s 0 2 0 1 ~715~1
- 3 - C 16 OR2 ! 0 4 0 8 :715
- 5 - C 16 OR2 ! 0 4 0 1 :724
- 1 - C 16 OR2 ! 0 3 0 39 :727
- 3 - C 21 OR2 ! 0 2 0 1 :738
- 4 - C 02 OR2 s 0 3 0 1 ~739~1
- 3 - C 06 OR2 ! 0 3 0 8 :739
- 4 - B 04 AND2 0 4 0 3 :802
- 3 - B 10 AND2 0 2 0 2 :809
- 1 - B 06 AND2 s ! 0 3 0 4 ~830~1
- 1 - A 03 AND2 s ! 0 3 0 13 ~830~2
- 1 - A 09 AND2 s ! 0 3 0 13 ~837~1
- 4 - B 10 AND2 s ! 0 3 0 2 ~844~1
- 3 - A 17 AND2 s 0 3 0 9 ~858~1
- 7 - A 15 AND2 s 0 3 0 9 ~865~1
- 5 - A 09 OR2 s 0 4 0 9 ~886~1
- 2 - A 09 OR2 s 0 4 0 9 ~893~1
- 2 - A 15 AND2 s ! 0 2 0 11 ~914~1
- 3 - B 23 OR2 ! 0 4 0 2 :928
- 4 - B 23 OR2 ! 0 4 0 2 :935
- 2 - B 21 OR2 s 0 3 0 5 ~942~1
- 5 - B 23 AND2 0 2 0 1 :942
- 3 - B 11 OR2 ! 0 2 0 1 :949
- 4 - B 11 AND2 0 4 0 2 :956
- 5 - B 11 AND2 0 4 0 2 :963
- 3 - A 12 AND2 s ! 0 4 0 4 ~970~1
- 3 - B 08 AND2 s ! 0 4 0 4 ~977~1
- 1 - B 09 AND2 s 0 4 0 4 ~998~1
- 2 - A 23 OR2 s 0 3 0 5 ~1026~1
- 1 - A 16 OR2 ! 0 4 0 2 :1040
- 2 - A 16 OR2 ! 0 4 0 2 :1047
- 3 - A 16 AND2 0 2 0 1 :1054
- 1 - A 11 OR2 ! 0 2 0 1 :1061
- 2 - A 11 OR2 ! 0 4 0 2 :1068
- 4 - A 11 OR2 ! 0 4 0 2 :1075
- 2 - A 12 AND2 s ! 0 2 0 6 ~1117~1
- 1 - A 13 AND2 s 0 3 0 6 ~1138~1
- 1 - A 12 OR2 s 0 3 0 7 ~1152~1
- 2 - A 03 AND2 s ! 0 2 0 12 ~1159~1
- 5 - A 04 AND2 s ! 0 2 0 6 ~1194~1
- 6 - A 10 AND2 s ! 0 2 0 7 ~1201~1
- 7 - A 14 OR2 s 0 2 0 1 ~1201~2
- 6 - A 14 OR2 s ! 0 2 0 1 ~1208~1
- 3 - A 08 OR2 s ! 0 3 0 2 ~1648~1
- 6 - B 07 AND2 ! 0 4 0 2 :1891
- 3 - A 07 AND2 ! 0 2 0 2 :1984
- 5 - A 06 OR2 s 0 3 0 1 ~2019~1
- 4 - A 16 AND2 s 0 2 0 2 ~2044~1
- 4 - B 07 OR2 ! 0 4 0 1 :2044
- 6 - B 24 OR2 s 0 2 0 2 ~2079~1
- 5 - B 08 OR2 s 0 3 0 1 ~2079~2
- 8 - B 07 OR2 ! 0 3 0 1 :2079
- 3 - A 15 OR2 s 0 4 0 3 ~2104~1
- 6 - B 04 AND2 s 0 2 0 1 ~2104~2
- 3 - A 21 OR2 ! 0 4 0 2 :2143
- 2 - A 02 OR2 s 0 3 0 3 ~2172~1
- 1 - A 07 AND2 s 0 3 0 2 ~2172~2
- 2 - A 07 OR2 0 3 0 1 :2173
- 6 - A 06 OR2 s ! 0 4 0 2 ~2202~1
- 1 - A 06 OR2 s ! 0 4 0 3 ~2202~2
- 7 - A 08 OR2 s ! 0 4 0 2 ~2202~3
- 6 - A 08 OR2 0 4 0 1 :2203
- 3 - A 01 OR2 s 0 3 0 2 ~2232~1
- 2 - A 01 AND2 s 0 2 0 2 ~2232~2
- 5 - B 07 AND2 s 0 3 0 3 ~2232~3
- 6 - B 08 OR2 s ! 0 3 0 2 ~2262~1
- 1 - B 08 OR2 s ! 0 4 0 2 ~2262~2
- 4 - B 24 OR2 s ! 0 2 0 3 ~2262~3
- 7 - B 07 OR2 0 4 0 1 :2262
- 1 - B 21 OR2 s 0 3 0 3 ~2292~1
- 5 - B 22 AND2 s 0 4 0 3 ~2292~2
- 7 - B 04 OR2 0 4 0 1 :2293
- 6 - A 07 OR2 ! 0 4 0 2 :2338
- 4 - A 07 OR2 ! 0 4 0 1 :2361
- 1 - A 05 OR2 s ! 0 4 0 3 ~2391~1
- 1 - A 10 OR2 s ! 0 4 0 2 ~2391~2
- 5 - A 07 OR2 ! 0 4 0 1 :2391
- 1 - A 01 OR2 s 0 3 0 3 ~2421~1
- 1 - B 07 OR2 s ! 0 3 0 2 ~2421~2
- 3 - B 02 OR2 ! 0 4 0 1 :2421
- 1 - B 11 OR2 s ! 0 2 0 2 ~2451~1
- 8 - B 24 OR2 ! 0 4 0 1 :2451
- 4 - A 17 OR2 s 0 4 0 3 ~2481~1
- 7 - B 24 OR2 s ! 0 3 0 1 ~2481~2
- 2 - B 24 OR2 ! 0 4 0 10 :2481
- 4 - A 03 OR2 ! 0 4 0 2 :2515
- 7 - A 06 OR2 s 0 3 0 1 ~2526~1
- 4 - A 06 OR2 ! 0 3 0 1 :2527
- 2 - A 04 OR2 s ! 0 3 0 3 ~2544~1
- 1 - A 02 OR2 s 0 3 0 4 ~2544~2
- 3 - A 06 OR2 ! 0 4 0 1 :2545
- 5 - A 11 AND2 s ! 0 2 0 4 ~2574~1
- 2 - A 06 OR2 ! 0 4 0 1 :2574
- 4 - A 01 OR2 ! 0 4 0 1 :2587
- 3 - B 07 OR2 s ! 0 2 0 1 ~2604~1
- 2 - B 07 AND2 s 0 2 0 4 ~2604~2
- 2 - B 08 OR2 ! 0 4 0 1 :2616
- 2 - B 23 AND2 s ! 0 2 0 5 ~2634~1
- 1 - B 24 OR2 s 0 3 0 2 ~2634~2
- 5 - B 24 OR2 ! 0 4 0 1 :2634
- 3 - B 24 OR2 ! 0 3 0 6 :2646
- 2 - A 21 OR2 s ! 0 4 0 3 ~2664~1
- 2 - A 18 OR2 s 0 4 0 4 ~2664~2
- 2 - B 22 OR2 ! 0 4 0 5 :2664
- 7 - B 05 OR2 ! 0 4 0 1 :2677
- 2 - A 14 OR2 ! 0 4 0 1 :2703
- 3 - A 14 OR2 ! 0 4 0 1 :2709
- 4 - A 14 OR2 ! 0 4 0 1 :2715
- 5 - A 14 OR2 ! 0 4 0 1 :2721
- 2 - A 08 OR2 ! 0 4 0 1 :2725
- 1 - A 14 OR2 ! 0 4 0 1 :2727
- 5 - A 08 OR2 ! 0 4 0 1 :2733
- 4 - A 08 OR2 ! 0 4 0 1 :2737
- 1 - A 08 OR2 ! 0 4 0 1 :2739
- 7 - A 11 OR2 ! 0 4 0 1 :2745
- 6 - A 11 OR2 ! 0 4 0 1 :2751
- 3 - A 11 OR2 ! 0 4 0 1 :2755
- 7 - A 16 OR2 ! 0 4 0 1 :2769
- 2 - A 05 OR2 ! 0 4 0 1 :2775
- 4 - B 08 OR2 ! 0 3 0 1 :2787
- 8 - B 08 OR2 ! 0 3 0 1 :2799
- 2 - B 11 OR2 ! 0 4 0 1 :2803
- 1 - B 23 OR2 ! 0 4 0 7 :2817
- 2 - A 24 OR2 ! 0 4 0 1 :2821
- 3 - B 18 OR2 ! 0 4 0 1 :2823
- 3 - A 24 OR2 ! 0 4 0 1 :2827
- 4 - A 24 OR2 ! 0 4 0 1 :2829
- 5 - A 24 OR2 ! 0 4 0 1 :2833
- 6 - A 24 OR2 ! 0 4 0 1 :2835
- 7 - A 24 OR2 ! 0 4 0 1 :2839
- 8 - A 24 OR2 ! 0 4 0 1 :2841
- 1 - A 24 OR2 ! 0 4 0 3 :2847
- 2 - C 19 OR2 0 3 0 5 :2887
- 7 - B 10 OR2 s ! 0 3 0 4 ~2914~1
- 2 - B 10 OR2 s ! 0 4 0 2 ~2914~2
- 8 - B 05 OR2 s ! 0 2 0 1 ~2914~3
- 2 - B 04 AND2 0 4 1 18 :2914
- 1 - B 10 OR2 s 0 3 0 4 ~2919~1
- 1 - B 04 OR2 s 0 4 0 2 ~2919~2
- 4 - B 05 OR2 ! 0 4 1 9 :2919
- 1 - B 05 OR2 s ! 0 4 0 1 ~2920~1
- 2 - B 05 OR2 s 0 4 0 2 ~2921~1
- 3 - B 05 OR2 s ! 0 4 0 1 ~2921~2
- 6 - B 05 OR2 ! 0 4 1 9 :2925
- 5 - B 05 OR2 s ! 0 3 0 1 ~2927~1
- 5 - C 02 OR2 s 0 3 0 2 ~2931~1
- 7 - C 18 OR2 s 0 2 0 2 ~2931~2
- 2 - C 01 OR2 s 0 3 0 1 ~2931~3
- 6 - C 18 OR2 s 0 3 0 2 ~2931~4
- 5 - C 18 OR2 s 0 4 0 1 ~2931~5
- 3 - C 18 OR2 s 0 4 0 1 ~2931~6
- 2 - C 18 OR2 s 0 4 0 1 ~2931~7
- 4 - C 18 OR2 s 0 4 0 1 ~2931~8
- 2 - C 12 OR2 s 0 3 0 2 ~2931~9
- 3 - C 12 OR2 s 0 4 0 1 ~2931~10
- 4 - C 12 OR2 s 0 4 0 1 ~2931~11
- 6 - C 12 OR2 s 0 3 0 1 ~2931~12
- 1 - C 18 OR2 s 0 4 0 1 ~2931~13
- 3 - C 02 OR2 s 0 4 0 1 ~2931~14
- 5 - C 12 OR2 s 0 4 0 1 ~2931~15
- 5 - B 04 OR2 ! 0 4 1 9 :2931
- 7 - C 12 AND2 s 0 4 0 1 ~2933~1
- 8 - C 18 OR2 s ! 0 3 0 3 ~2933~2
- 6 - C 02 AND2 s 0 4 0 1 ~2933~3
- 3 - B 01 OR2 s 0 3 0 4 ~2933~4
- 4 - B 12 OR2 s 0 2 0 2 ~2933~5
- 3 - B 04 OR2 s ! 0 4 0 1 ~2933~6
- 3 - B 14 AND2 0 4 0 6 :2950
- 1 - B 13 OR2 ! 0 4 0 5 :2955
- 1 - B 19 AND2 s 0 3 0 1 ~2960~1
- 5 - B 13 AND2 0 4 0 3 :2960
- 7 - B 13 AND2 0 4 0 2 :2965
- 6 - B 21 OR2 ! 0 4 0 5 :2970
- 1 - B 20 AND2 0 4 0 7 :2985
- 3 - B 19 OR2 s ! 0 3 0 1 ~2995~1
- 2 - B 16 AND2 0 4 0 3 :3000
- 2 - B 14 OR2 ! 0 4 0 6 :3005
- 4 - B 17 AND2 0 4 0 3 :3010
- 1 - B 18 OR2 ! 0 4 0 4 :3015
- 5 - B 16 AND2 0 4 0 1 :3025
- 7 - B 17 OR2 0 3 0 1 :3065
- 1 - B 17 OR2 0 4 0 1 :3095
- 3 - C 14 OR2 s 0 3 0 2 ~3117~1
- 2 - C 14 OR2 s ! 0 2 0 2 ~3131~1
- 5 - C 14 OR2 0 4 1 0 :3131
- 8 - B 17 AND2 0 3 0 2 :3138
- 2 - B 17 AND2 0 2 0 2 :3146
- 6 - B 16 AND2 s 0 3 0 2 ~3156~1
- 1 - B 16 OR2 s 0 2 0 5 ~3156~2
- 6 - B 17 OR2 s 0 2 0 1 ~3156~3
- 5 - B 17 OR2 0 4 0 1 :3164
- 5 - C 15 OR2 0 4 1 0 :3180
- 3 - C 15 OR2 s ! 0 2 0 2 ~3182~1
- 4 - B 16 OR2 0 4 0 1 :3201
- 2 - B 19 OR2 0 4 0 1 :3215
- 8 - B 19 OR2 0 4 0 1 :3225
- 4 - B 19 OR2 s 0 4 0 1 ~3227~1
- 3 - C 24 OR2 0 3 1 0 :3231
- 7 - B 16 OR2 s 0 4 0 2 ~3249~1
- 3 - B 16 OR2 0 4 0 1 :3258
- 7 - B 20 OR2 0 4 0 1 :3275
- 3 - C 13 OR2 0 4 1 0 :3282
- 1 - B 22 OR2 s 0 4 0 1 ~3324~1
- 2 - C 15 OR2 s 0 2 0 1 ~3324~2
- 1 - C 14 OR2 0 4 1 0 :3333
- 2 - B 15 OR2 s 0 2 0 1 ~3363~1
- 2 - B 18 OR2 0 4 0 1 :3374
- 1 - C 15 OR2 0 4 1 0 :3384
- 3 - B 17 OR2 0 3 0 1 :3407
- 8 - B 14 OR2 s 0 4 0 5 ~3420~1
- 1 - B 15 OR2 0 4 0 1 :3428
- 1 - C 19 OR2 s 0 2 0 3 ~3429~1
- 7 - B 15 OR2 0 4 1 0 :3435
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\lu\vhdl-digitallogic\disk\ch7\timer_dsp.rpt
timer_dspa
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 23/ 96( 23%) 13/ 48( 27%) 3/ 48( 6%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
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