eth_wishbone.v

这是一个很好的Verilog 编写的8位RISC CPU源码（可做为MCU）

  if(SetWriteRxDataToFifo & ~RxAbort)
    WriteRxDataToFifo <=#Tp 1'b1;
  else
  if(WriteRxDataToFifoSync2 | RxAbort)
    WriteRxDataToFifo <=#Tp 1'b0;
end



always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    WriteRxDataToFifoSync1 <=#Tp 1'b0;
  else
  if(WriteRxDataToFifo)
    WriteRxDataToFifoSync1 <=#Tp 1'b1;
  else
    WriteRxDataToFifoSync1 <=#Tp 1'b0;
end

always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    WriteRxDataToFifoSync2 <=#Tp 1'b0;
  else
    WriteRxDataToFifoSync2 <=#Tp WriteRxDataToFifoSync1;
end

always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    WriteRxDataToFifoSync3 <=#Tp 1'b0;
  else
    WriteRxDataToFifoSync3 <=#Tp WriteRxDataToFifoSync2;
end

wire WriteRxDataToFifo_wb;
assign WriteRxDataToFifo_wb = WriteRxDataToFifoSync2 & ~WriteRxDataToFifoSync3;


reg LatchedRxStartFrm;
reg SyncRxStartFrm;
reg SyncRxStartFrm_q;
reg SyncRxStartFrm_q2;
wire RxFifoReset;

always @ (posedge MRxClk or posedge Reset)
begin
  if(Reset)
    LatchedRxStartFrm <=#Tp 0;
  else
  if(RxStartFrm & ~SyncRxStartFrm_q)
    LatchedRxStartFrm <=#Tp 1;
  else
  if(SyncRxStartFrm_q)
    LatchedRxStartFrm <=#Tp 0;
end


always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    SyncRxStartFrm <=#Tp 0;
  else
  if(LatchedRxStartFrm)
    SyncRxStartFrm <=#Tp 1;
  else
    SyncRxStartFrm <=#Tp 0;
end


always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    SyncRxStartFrm_q <=#Tp 0;
  else
    SyncRxStartFrm_q <=#Tp SyncRxStartFrm;
end

always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    SyncRxStartFrm_q2 <=#Tp 0;
  else
    SyncRxStartFrm_q2 <=#Tp SyncRxStartFrm_q;
end


assign RxFifoReset = SyncRxStartFrm_q & ~SyncRxStartFrm_q2;

wire [4:0] rxfifo_cnt;

eth_fifo #(`RX_FIFO_DATA_WIDTH, `RX_FIFO_DEPTH, `RX_FIFO_CNT_WIDTH)
rx_fifo (.data_in(RxDataLatched2),                      .data_out(m_wb_dat_o), 
         .clk(WB_CLK_I),                                .reset(Reset), 
         .write(WriteRxDataToFifo_wb),                  .read(MasterWbRX & m_wb_ack_i), 
         .clear(RxFifoReset),                           .full(RxBufferFull), 
         .almost_full(),                                .almost_empty(RxBufferAlmostEmpty), 
         .empty(RxBufferEmpty),                         .cnt(rxfifo_cnt)
        );

assign WriteRxDataToMemory = ~RxBufferEmpty & ~MasterWbRX;



// Generation of the end-of-frame signal
always @ (posedge MRxClk or posedge Reset)
begin
  if(Reset)
    ShiftEnded_tck <=#Tp 1'b0;
  else
  if(~RxAbort & SetWriteRxDataToFifo & StartShiftWillEnd)
    ShiftEnded_tck <=#Tp 1'b1;
  else
  if(RxAbort | ShiftEndedSync_c1 & ShiftEndedSync_c2)
    ShiftEnded_tck <=#Tp 1'b0;
end

always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    ShiftEndedSync1 <=#Tp 1'b0;
  else
    ShiftEndedSync1 <=#Tp ShiftEnded_tck;
end

always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    ShiftEndedSync2 <=#Tp 1'b0;
  else
    ShiftEndedSync2 <=#Tp ShiftEndedSync1;
end

always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    ShiftEndedSync3 <=#Tp 1'b0;
  else
  if(ShiftEndedSync1 & ~ShiftEndedSync2)
    ShiftEndedSync3 <=#Tp 1'b1;
  else
  if(ShiftEnded)
    ShiftEndedSync3 <=#Tp 1'b0;
end

// Generation of the end-of-frame signal
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    ShiftEnded <=#Tp 1'b0;
  else
  if(ShiftEndedSync3 & MasterWbRX & m_wb_ack_i & RxBufferAlmostEmpty & ~ShiftEnded)
    ShiftEnded <=#Tp 1'b1;
  else
  if(RxStatusWrite)
    ShiftEnded <=#Tp 1'b0;
end

always @ (posedge MRxClk or posedge Reset)
begin
  if(Reset)
    ShiftEndedSync_c1 <=#Tp 1'b0;
  else
    ShiftEndedSync_c1 <=#Tp ShiftEndedSync2;
end

always @ (posedge MRxClk or posedge Reset)
begin
  if(Reset)
    ShiftEndedSync_c2 <=#Tp 1'b0;
  else
    ShiftEndedSync_c2 <=#Tp ShiftEndedSync_c1;
end

// Generation of the end-of-frame signal
always @ (posedge MRxClk or posedge Reset)
begin
  if(Reset)
    RxEnableWindow <=#Tp 1'b0;
  else
  if(RxStartFrm)
    RxEnableWindow <=#Tp 1'b1;
  else
  if(RxEndFrm | RxAbort)
    RxEnableWindow <=#Tp 1'b0;
end


always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    RxAbortSync1 <=#Tp 1'b0;
  else
//    RxAbortSync1 <=#Tp RxAbort;
    RxAbortSync1 <=#Tp RxAbortLatched;
end

always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    RxAbortSync2 <=#Tp 1'b0;
  else
    RxAbortSync2 <=#Tp RxAbortSync1;
end

always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    RxAbortSync3 <=#Tp 1'b0;
  else
    RxAbortSync3 <=#Tp RxAbortSync2;
end

always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    RxAbortSync4 <=#Tp 1'b0;
  else
    RxAbortSync4 <=#Tp RxAbortSync3;
end

always @ (posedge MRxClk or posedge Reset)
begin
  if(Reset)
    RxAbortSyncb1 <=#Tp 1'b0;
  else
    RxAbortSyncb1 <=#Tp RxAbortSync2;
end

always @ (posedge MRxClk or posedge Reset)
begin
  if(Reset)
    RxAbortSyncb2 <=#Tp 1'b0;
  else
    RxAbortSyncb2 <=#Tp RxAbortSyncb1;
end


always @ (posedge MRxClk or posedge Reset)
begin
  if(Reset)
    RxAbortLatched <=#Tp 1'b0;
  else
  if(RxAbortSyncb2)
    RxAbortLatched <=#Tp 1'b0;
  else
  if(RxAbort)
    RxAbortLatched <=#Tp 1'b1;
end

/*
reg LoadStatusBlocked;

always @ (posedge MRxClk or posedge Reset)
begin
  if(Reset)
    LoadStatusBlocked <=#Tp 1'b0;
  else
  if(LoadRxStatus & ~RxAbortLatched)
    LoadStatusBlocked <=#Tp 1'b1;
  else
  if(RxStatusWrite_rck | RxStartFrm)
    LoadStatusBlocked <=#Tp 1'b0;
end
*/
// LatchedRxLength[15:0]
always @ (posedge MRxClk or posedge Reset)
begin
  if(Reset)
    LatchedRxLength[15:0] <=#Tp 16'h0;
  else
//  if(LoadRxStatus & ~RxAbortLatched & ~LoadStatusBlocked)
  if(LoadRxStatus)
    LatchedRxLength[15:0] <=#Tp RxLength[15:0];
end


assign RxStatusIn = {RxOverrun, InvalidSymbol, DribbleNibble, ReceivedPacketTooBig, ShortFrame, LatchedCrcError, RxLateCollision};

always @ (posedge MRxClk or posedge Reset)
begin
  if(Reset)
    RxStatusInLatched <=#Tp 'h0;
  else
//  if(LoadRxStatus & ~RxAbortLatched & ~LoadStatusBlocked)
  if(LoadRxStatus)
    RxStatusInLatched <=#Tp RxStatusIn;
end


// Rx overrun
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    RxOverrun <=#Tp 1'b0;
  else
  if(RxStatusWrite)
    RxOverrun <=#Tp 1'b0;
  else
  if(RxBufferFull & WriteRxDataToFifo_wb)
    RxOverrun <=#Tp 1'b1;
end



wire TxError;
assign TxError = TxUnderRun | RetryLimit | LateCollLatched | CarrierSenseLost;

wire RxError;
assign RxError = |RxStatusInLatched[6:0];

// Tx Done Interrupt
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    TxB_IRQ <=#Tp 1'b0;
  else
  if(TxStatusWrite & TxIRQEn)
    TxB_IRQ <=#Tp ~TxError;
  else
    TxB_IRQ <=#Tp 1'b0;
end


// Tx Error Interrupt
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    TxE_IRQ <=#Tp 1'b0;
  else
  if(TxStatusWrite & TxIRQEn)
    TxE_IRQ <=#Tp TxError;
  else
    TxE_IRQ <=#Tp 1'b0;
end


// Rx Done Interrupt
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    RxB_IRQ <=#Tp 1'b0;
  else
  if(RxStatusWrite & RxIRQEn)
    RxB_IRQ <=#Tp ReceivedPacketGood;
  else
    RxB_IRQ <=#Tp 1'b0;
end


// Rx Error Interrupt
always @ (posedge WB_CLK_I or posedge Reset)
begin
  if(Reset)
    RxE_IRQ <=#Tp 1'b0;
  else
  if(RxStatusWrite & RxIRQEn)
    RxE_IRQ <=#Tp RxError;
  else
    RxE_IRQ <=#Tp 1'b0;
end


assign Busy_IRQ = 1'b0;




         
// TX
// bit 15 ready
// bit 14 interrupt
// bit 13 wrap
// bit 12 pad
// bit 11 crc
// bit 10 last
// bit 9  pause request (control frame)
// bit 8  TxUnderRun          
// bit 7-4 RetryCntLatched    
// bit 3  retransmittion limit
// bit 2  LateCollLatched        
// bit 1  DeferLatched        
// bit 0  CarrierSenseLost    


// RX
// bit 15 od rx je empty
// bit 14 od rx je interrupt
// bit 13 od rx je wrap
// bit 12 od rx je reserved
// bit 11 od rx je reserved
// bit 10 od rx je reserved
// bit 9  od rx je reserved
// bit 8  od rx je reserved
// bit 7  od rx je Miss
// bit 6  od rx je RxOverrun
// bit 5  od rx je InvalidSymbol
// bit 4  od rx je DribbleNibble
// bit 3  od rx je ReceivedPacketTooBig
// bit 2  od rx je ShortFrame
// bit 1  od rx je LatchedCrcError
// bit 0  od rx je RxLateCollision

assign reg1 = RxPointer[31:0];                  /* 0x58 */

assign reg2 = {                                 /* 0x5c */
  RxStatusWriteLatched,         // 31
  RxStatusWrite_rck,            // 30
  RxEn_needed,                  // 29
  StartRxBDRead,                // 28
  RxStatusWrite,                // 27
  1'b1, //RxAbortLatched,               // 26
  RxBDRead,                     // 25
  RxBDReady,                    // 24
  ShiftEnded,                   // 23
  RxPointerRead,                // 23
  LastByteIn,                   // 21
  ShiftWillEnd,                 // 20
  2'h0, RxByteCnt[1:0],         // 19:16
  2'h0, RxPointerLatched[1:0],  // 15:12
  RxBDAddress[7:0],             // 11:4
  state[3:0]                    // 3:0
};

assign reg3 = {                                 /* 0x60 */
  ShiftEndedSync_c2,            // 31
  RxAbortSyncb1,                // 30
  RxAbortSyncb2,                // 31
  RxAbortSync1,                 // 30
  RxAbortSync2,                 // 29
  1'b0, //LoadStatusBlocked,            // 28
  LoadRxStatus,                 // 27
  1'b0, //LoadStatusBlocked,            // 26
  RxOverrun,                    // 25
  RxAbort,                      // 24
  RxValid,                      // 23
  RxEndFrm,                     // 22
  RxEnableWindow,               // 21
  StartShiftWillEnd,            // 20
  ShiftWillEnd,                 // 19
  ShiftEnded_tck,               // 18
  SetWriteRxDataToFifo,         // 17
  WriteRxDataToFifo,            // 16
  WriteRxDataToFifoSync3,       // 15
  WriteRxDataToFifoSync2,       // 14
  WriteRxDataToFifoSync1,       // 13
  WriteRxDataToFifo_wb,         // 12
  LatchedRxStartFrm,            // 11
  RxStartFrm,                   // 10
  SyncRxStartFrm,               // 9
  SyncRxStartFrm_q,             // 8
  SyncRxStartFrm_q2,            // 7
  RxBufferEmpty,                // 6
  RxBufferFull,                 // 5
  rxfifo_cnt[4:0]               // 4:0
};

assign reg4 = {                                 /* 0x64 */
  WriteRxDataToMemory,          // 4
  ShiftEndedSync1,              // 3
  ShiftEndedSync2,              // 2
  ShiftEndedSync3,              // 1
  ShiftEndedSync_c1             // 0
};


endmodule