interleave.v

块交织的verilog代码

module interleave(clk_data,mcu_reset,con1_valid,con2_out,
			   encode_out,int_valid);	  

	parameter HALF_N=3;		
	parameter N=6;			//N=2*HALF_N
	parameter BLOCK_SIZE = 64;// BLOCK_SIZE=2^N

    input clk_data;
    input mcu_reset;  //the system  reset
    input con1_valid;
    input [1:0]con2_out;

    output [1:0]encode_out;
    output int_valid;

    reg sign;
    reg int_valid;
    reg[(BLOCK_SIZE-1):0] block0,block1;
    reg[(N-1):0] counter;
    reg [1:0]encode_out;	     

	always @ (posedge clk_data or posedge mcu_reset)
	begin
	if(mcu_reset)
	begin
			sign<=0;
			int_valid<=0;
			counter<=0;
			block0<=0;
			block1<=0;
			encode_out<=2'b00;
	end
	else
	begin
		if(con1_valid==0)
		begin
			sign<=0;
			int_valid<=0;
			counter<=0;
		end
		else
		begin   
			counter<=counter+2;			
			if(sign==0)		   //write block0,read block1
				begin
					block0[counter]<=con2_out[0];
					block0[counter+1]<=con2_out[1];
					encode_out[0]<=block1[{counter[(HALF_N-1):0],counter[(N-1):HALF_N]}];
					encode_out[1]<=block1[{counter[(HALF_N-1):0]+1,counter[(N-1):HALF_N]}];
				end
			else				   //wtite block1,read block0
				begin
					block1[counter]<=con2_out[0];
					block1[counter+1]<=con2_out[1];
					encode_out[0]<=block0[{counter[(HALF_N-1):0],counter[(N-1):HALF_N]}];
					encode_out[1]<=block0[{counter[(HALF_N-1):0]+1,counter[(N-1):HALF_N]}];
				end
			if(counter==(BLOCK_SIZE-2))
			begin
				if (sign==0)
					begin
						int_valid<=1;
						sign<=1;
					end
				else
					sign<=0;
			end

		end
	end		
	end
endmodule