top.vhd

脉冲多普勒雷达回波信号相干积累的VHDL源程序

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity top is
    Port ( gClk : in std_logic;		  								--全局时钟
	 		  gRst : in std_logic;										--全局复位
	 		  frame : in std_logic;										--桢同步
           frameDelay : in std_logic_vector(6 downto 0);		--桢延时
           sampleInterval : in std_logic_vector(6 downto 0);--采样脉冲间隔
           sampleNum : in std_logic_vector(6 downto 0);		--采样脉冲个数
           groupNum : in std_logic_vector(6 downto 0);		--采样组数
           start : in std_logic;										--采样开始
           dspRead : in std_logic;									--dsp读取累加数据
			  I : in std_logic_vector(13 downto 0);				--I
			  Q : in std_logic_vector(13 downto 0);				--Q
           readEn : out std_logic);									--存储器读取使能
end top;

architecture Behavioral of top is

	type stateMachine1 is (sm1Idle,sm1Frame,sm1Cnt,sm1CntEnd,sm1AddrClr);
	signal smMain : stateMachine1;

	type stateMachine2 is (sm2Idle,sm2RM,sm2RM1,sm2Add,sm2Add1,sm2WM,sm2WM1,sm2WM2,sm2WM3);
	signal smRam : stateMachine2;

	component ramiq												  		
	   PORT (
		addr: IN std_logic_VECTOR(6 downto 0);						
		clk: IN std_logic;
		din: IN std_logic_VECTOR(26 downto 0);
		dout: OUT std_logic_VECTOR(26 downto 0);
		we: IN std_logic);
	end component;

	signal cntRamIAddrQ : std_logic_vector(6 downto 0) :=(others=>'0');		--ramI地址计数器输出
	signal cntRamIAddrEn : std_logic :='0';								--ramI地址计数器使能
	signal cntRamIAddrClr : std_logic :='0';		--ramI地址计数器清零

	signal sRamIClk : std_logic := '0';										--ramI时钟
	signal sRamIDin : std_logic_vector(26 downto 0) :=(others=>'0');			--ramI数据输入
	signal sRamIDout : std_logic_vector(26 downto 0) :=(others=>'0');			--ramI数据输出
	signal sRamIWe : std_logic :='0';										--ramI读写信号 ‘1’-写；‘0’-读
	
	signal presentValue : std_logic_vector(26 downto 0) :=(others=>'0'); 		--当前累加寄存器的值

	signal readRamI : std_logic :='0';										--主进程通知ramI读写进程进行读操作

	signal cntFrameDelayEn : std_logic :='0';								--桢延迟计数器使能
	signal cntFrameDelayQ : std_logic_vector(6 downto 0) :=(others=>'0');		--桢延迟计数器输出

	signal cntSampleIntervalEn : std_logic :='0';								--采样脉冲间隔计数器使能
	signal cntSampleIntervalQ : std_logic_vector(6 downto 0) :=(others=>'0');		--采样脉冲间隔计数器输出

	signal cntGroupNumEn : std_logic :='0';		--采样组数计数器使能
	signal cntGroupNumQ : std_logic_vector(6 downto 0) :=(others=>'0');		--采样组数计数器输出
--	signal bReadRamFinish : boolean := false;

begin

	ramIInst : ramiq
		port map(
			addr=>cntRamIAddrQ,
			clk=>sRamIClk,
			din=>sRamIDin,
			dout=>sRamIDout,
			we=>sRamIWe);

	pSmMain : process(gClk)									  	--主状态机
	begin
		if gClk'event and gClk='1' then
			case smMain	is 
				when sm1Idle=>							 --如果采样到桢同步，则桢延时计数器开始记数	
					if frame='1' then										 
						cntFrameDelayEn<='1';			 --桢延迟计数器开始计时
						cntGroupNumEn<='1';		--采样组数计数器+1
						smMain<=sm1Frame;
					else											 --否则，仍保持空闲状态
						smMain<=sm1Idle;
					end if;
				when sm1Frame=>
					cntGroupNumEn<='0';		--采样组数计数器停止
					if cntFrameDelayQ=frameDelay then				 --达到延迟时间，
						cntFrameDelayEn<='0';				 --将桢延迟计数器清零
						smMain<=sm1Cnt;
					else
						smMain<=sm1Frame;
					end if;
				when sm1Cnt=>
					readRamI<='1';						 --触发存储器读写状态机进行读操作		
					cntSampleIntervalEn<='1';			 --同时开始采样脉冲延时记数器	
					smMain<=sm1CntEnd;			
				when sm1CntEnd=>
					readRamI<='0';
					if cntSampleIntervalQ=sampleInterval then	 --达到采样间隔时间,采样IQ值并进行累加
						cntSampleIntervalEn<='0';		--采样脉冲间隔计数器清零
						smMain<=sm1Cnt;
					elsif cntRamIAddrQ=sampleNum then		--如果采样脉达到规定个数
						cntSampleIntervalEn<='0';		--采样脉冲间隔计数器清零
						cntRamIAddrClr<='1';	   	--把ramI地址寄存器清零
						smMain<=sm1AddrClr;
					else
						smMain<=sm1CntEnd;
					end if;
				when sm1AddrClr=>
					cntRamIAddrClr<='0';
					smMain<=sm1Idle;
			end case;
		end if;
	end process pSmMain;

	pSmRam : process(gClk)		--存储器读写状态机
	begin
		case smRam is
			when sm2Idle=>
				if gClk'event and gClk='1' then
					if readRamI='1' then		--开始进行读存储器操作
						smRam<=sm2RM;
					end if;
				end if;
			when sm2RM=>												 
				sRamIWe<='0';		--读ramI													
				smRam<=sm2RM1;
			when sm2RM1=>
				sRamIClk<='1';
				smRam<=sm2Add;
			when sm2Add=>
				presentValue<=sRamIDout;
				smRam<=sm2Add1;
			when sm2Add1=>
				presentValue<=presentValue+I;		--数据累加
				smRam<=sm2WM;
 			when sm2WM=>
				sRamIDin<=presentValue;
				sRamIClk<='0';
				sRamIWe<='1';		--写ramI
				smRam<=sm2WM1;
			when sm2WM1=>
				sRamIClk<='1';
				smRam<=sm2WM2;
			when sm2WM2=>
				sRamIClk<='0';
				sRamIWe<='0';
				cntRamIAddrEn<='1';		--ramI地址计数器+1
				smRam<=sm2WM3;
			when sm2WM3=>
				cntRamIAddrEn<='0';
				smRam<=sm2Idle;
		end case;
	end process pSmRam;							
				
	pFrameDelay : process(gClk)										  --桢延迟计数器
	begin
		if gClk'event and gClk='1' then
			if cntFrameDelayEn='1' then
				cntFrameDelayQ<=cntFrameDelayQ+1;
			else
				cntFrameDelayQ<=(others=>'0');
			end if;
		end if;
	end process pFrameDelay;									

	pSampleInterval : process(gClk)										--采样脉冲间隔计数器
	begin
		if gClk'event and gClk='1' then
			if cntSampleIntervalEn='1' then
				cntSampleIntervalQ<=cntSampleIntervalQ+1;
			else
				cntSampleIntervalQ<=(others=>'0');
			end if;
		end if;
	end process pSampleInterval;	
	
	pCntRamIAddr : process(gClk,cntRamIAddrClr)		--ramI地址计数器
	begin
		if cntRamIAddrClr='1' then
			cntRamIAddrQ<=(others=>'0');
		elsif gClk'event and gClk='1' then
			if cntRamIAddrEn='1' then
				cntRamIAddrQ<=cntRamIAddrQ+1;
			else
				cntRamIAddrQ<=cntRamIAddrQ;
			end if;
		end if;
	end process pCntRamIAddr;
	
	pGroupNum : process(gClk)										  --采样组数计数器
	begin
		if gClk'event and gClk='1' then
			if cntGroupNumEn='1' then
				cntGroupNumQ<=cntGroupNumQ+1;
			else
				cntGroupNumQ<=(others=>'0');
			end if;
		end if;
	end process pGroupNum;									
								
end Behavioral;