mymima.vhd

密码锁的VHDL程序

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity mima is
    Port ( key : in std_logic_vector(7 downto 0);--键值输入7～0对应8～1
           clk : in std_logic;--时序基本时钟暂定2048hz
           sel : out std_logic_vector(2 downto 0):="000";--数码管的片选
		 
           ledout : out std_logic_vector(6 downto 0));--数码管显示

end mima;

architecture Behavioral of mima is
type state_value is (st0,st1,st2,st3,st4,st5);
signal pre_state,next_state: state_value:=st0;
signal key_out:std_logic_vector(3 downto 0);--处理后的键值0表示什么键都没有按下
signal sample_clk:std_logic;
signal sled: std_logic_vector (6 downto 0);

begin

sample_gne: block
	signal q: std_logic_vector(3 downto 0):="0000";
begin
	process(clk)
	begin
		if rising_edge(clk) then
		q<=q+1;
		end if;
	end process;
sample_clk<=q(3);

end block sample_gne;

doudong:block
	signal nkey,d0,d1,s,r,q,nq,temp1,temp0,key_1:std_logic_vector(7 downto 0);
begin
	process(sample_clk)
	begin
		if rising_edge(sample_clk) then
		d1<=d0;d0<=nkey;
		temp1<=temp0;temp0<=q;
		end if;
	end process;
	s<=d0 and d1;
	r<=not d0 and not d1;
	q<=r nor nq;
	nq<=s nor q;
	nkey<=not key;
	key_1<=temp0 and not temp1;
	process(key_1)
	begin
	case key_1 is
	when "10000000"=> key_out<="1000";
	when "01000000"=> key_out<="0111";
	when "00100000"=> key_out<="0110";
	when "00010000"=> key_out<="0101";
	when "00001000"=> key_out<="0100";
	when "00000100"=> key_out<="0011";
	when "00000010"=> key_out<="0010";
	when "00000001"=> key_out<="0001";
	when "00000000"=> key_out<="0000";
	when others =>	key_out<="0000";
	end case;
	end process;

end block doudong;

state_switch: process(sample_clk)
begin
	if rising_edge(sample_clk) then
		pre_state<=next_state;
	end if;
end  process state_switch;

state_change: process(key_out,pre_state)
begin
	case pre_state is
	when st0 => sled<="0111111";--"1000000"数码管显示没有通过'0'
			  case key_out is
			  	when "0011" =>next_state<=st1;
				when others =>next_state<=st0;
			  end case;
     when st1 => sled<="0000110";--"1111001"; -- 1数码管显示没有通过
			  case key_out is
			  	when "0000" =>next_state<=st1;
			  	when "0101" =>next_state<=st2;
				when others =>next_state<=st0;
			  end case;
     when st2 => sled<="1011011";--"0100100"; -- 2数码管显示没有通过
			  case key_out is
			  	when "0000" =>next_state<=st2;
			  	when "0110" =>next_state<=st3;
				when others =>next_state<=st0;
			  end case;
     when st3 => sled<="1001111";--"0110000"; -- 3数码管显示没有通过
			  case key_out is
			  	when "0000" =>next_state<=st3;
			  	when "0111" =>next_state<=st4;
				when others =>next_state<=st0;
			  end case;
	when st4 => sled<="1100110";--"0011001"; -- 4数码管显示没有通过
			  case key_out is
			  	when "0000" =>next_state<=st4;
			  	when "1000" =>next_state<=st5;
				when others =>next_state<=st0;
			  end case;
	when st5 => sled<="1110011";--数码管显示通过
			  case key_out is
			  	when "0000" =>next_state<=st5;
			  	
				when others =>next_state<=st0;
			  end case;
			  
	when others=> null;
     end case;
end process state_change;
sel<="000";
ledout<=sled;	

--key_out11<=key_out;
end Behavioral;