ddsqam.xco

基于FPGA的16QAM调制与解调的设计与实现源代码

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#
# Xilinx Core Generator version J.40
# Date: Tue May 20 01:51:50 2008
#
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#
#  This file contains the customisation parameters for a
#  Xilinx CORE Generator IP GUI. It is strongly recommended
#  that you do not manually alter this file as it may cause
#  unexpected and unsupported behavior.
#
##############################################################
#
# BEGIN Project Options
SET addpads = False
SET asysymbol = True
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = False
SET designentry = VHDL
SET device = xc4vsx35
SET devicefamily = virtex4
SET flowvendor = Foundation_iSE
SET formalverification = False
SET foundationsym = False
SET implementationfiletype = Ngc
SET package = ff668
SET removerpms = False
SET simulationfiles = Behavioral
SET speedgrade = -10
SET verilogsim = True
SET vhdlsim = True
# END Project Options
# BEGIN Select
SELECT Direct_Digital_Synthesizer family Xilinx,_Inc. 5.0
# END Select
# BEGIN Parameters
CSET accumulator_latency=One_Cycle
CSET aclr_pin=false
CSET channel_pin=false
CSET channels=1
CSET clock_enable=true
CSET component_name=ddsqam
CSET create_rpm=false
CSET dds_clock_rate=12.5
CSET frequency_resolution=0.4
CSET memory_type=Auto
CSET negative_cosine=false
CSET negative_sine=false
CSET noise_shaping=Auto
CSET output_frequencies=1.0
CSET outputs_required=Sine_and_Cosine
CSET phase_increment=Programmable
CSET phase_offset=Programmable
CSET phase_offset_angles=0.0
CSET pipelined=true
CSET rdy_pin=false
CSET rfd_pin=false
CSET sclr_pin=false
CSET spurious_free_dynamic_range=96.0
# END Parameters
GENERATE
# CRC: b3ae843c