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📄 ddsqam.vhd

📁 基于FPGA的16QAM调制与解调的设计与实现源代码
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         c_has_sinit => 0,
         c_has_q => 1,
         c_has_o => 1,
         c_inputs => 2,
         c_input_inv_mask => "00"
      )
      PORT MAP (
         I => BU560_I,
         T => BU560_T,
         EN => BU560_EN,
         Q => BU560_Q,
         CLK => BU560_CLK,
         CE => BU560_CE,
         ACLR => BU560_ACLR,
         ASET => BU560_ASET,
         AINIT => BU560_AINIT,
         SCLR => BU560_SCLR,
         SSET => BU560_SSET,
         SINIT => BU560_SINIT,
         O => BU560_O
      );

   BU565_CLK <= n175;
   BU565_SDIN <= n1812;
   n1813 <= BU565_Q(0);
   n1804 <= BU565_Q(7);
   n1805 <= BU565_Q(8);
   n1806 <= BU565_Q(9);
   n1807 <= BU565_Q(10);
   n1808 <= BU565_Q(11);
   n1809 <= BU565_Q(12);
   n1810 <= BU565_Q(13);
   n1811 <= BU565_Q(14);
   BU565_CE <= n176;
   BU565 : C_SHIFT_FD_V7_0
      GENERIC MAP (
         c_has_aset => 0,
         c_has_d => 0,
         c_sync_priority => 0,
         c_has_sclr => 0,
         c_fill_data => 5,
         c_width => 15,
         c_enable_rlocs => 0,
         c_ainit_val => "100000000000000",
         c_has_ce => 1,
         c_has_aclr => 0,
         c_sync_enable => 0,
         c_has_ainit => 0,
         c_has_sdout => 0,
         c_sinit_val => "100000000000000",
         c_has_sset => 0,
         c_has_sinit => 0,
         c_has_q => 1,
         c_shift_type => 0,
         c_has_sdin => 1,
         c_has_lsb_2_msb => 0
      )
      PORT MAP (
         CLK => BU565_CLK,
         SDIN => BU565_SDIN,
         Q => BU565_Q,
         CE => BU565_CE
      );

   BU598_I(0) <= n1859;
   BU598_I(1) <= n1860;
   BU598_I(2) <= n1853;
   BU598_I(3) <= n1857;
   BU598_T <= '0';
   BU598_EN <= '0';
   BU598_CLK <= '0';
   BU598_CE <= '0';
   BU598_ACLR <= '0';
   BU598_ASET <= '0';
   BU598_AINIT <= '0';
   BU598_SCLR <= '0';
   BU598_SSET <= '0';
   BU598_SINIT <= '0';
   n1858 <= BU598_O;
   BU598 : C_GATE_BIT_V7_0
      GENERIC MAP (
         c_has_aset => 0,
         c_gate_type => 4,
         c_sync_priority => 1,
         c_has_sclr => 0,
         c_enable_rlocs => 0,
         c_ainit_val => "0",
         c_pipe_stages => 0,
         c_has_ce => 0,
         c_has_aclr => 0,
         c_sync_enable => 0,
         c_has_ainit => 0,
         c_sinit_val => "0",
         c_has_sset => 0,
         c_has_sinit => 0,
         c_has_q => 1,
         c_has_o => 1,
         c_inputs => 4,
         c_input_inv_mask => "0000"
      )
      PORT MAP (
         I => BU598_I,
         T => BU598_T,
         EN => BU598_EN,
         Q => BU598_Q,
         CLK => BU598_CLK,
         CE => BU598_CE,
         ACLR => BU598_ACLR,
         ASET => BU598_ASET,
         AINIT => BU598_AINIT,
         SCLR => BU598_SCLR,
         SSET => BU598_SSET,
         SINIT => BU598_SINIT,
         O => BU598_O
      );

   BU603_CLK <= n175;
   BU603_SDIN <= n1858;
   n1859 <= BU603_Q(0);
   n1860 <= BU603_Q(2);
   n1850 <= BU603_Q(8);
   n1851 <= BU603_Q(9);
   n1852 <= BU603_Q(10);
   n1853 <= BU603_Q(11);
   n1854 <= BU603_Q(12);
   n1855 <= BU603_Q(13);
   n1856 <= BU603_Q(14);
   n1857 <= BU603_Q(15);
   BU603_CE <= n176;
   BU603 : C_SHIFT_FD_V7_0
      GENERIC MAP (
         c_has_aset => 0,
         c_has_d => 0,
         c_sync_priority => 0,
         c_has_sclr => 0,
         c_fill_data => 5,
         c_width => 16,
         c_enable_rlocs => 0,
         c_ainit_val => "1000000000000000",
         c_has_ce => 1,
         c_has_aclr => 0,
         c_sync_enable => 0,
         c_has_ainit => 0,
         c_has_sdout => 0,
         c_sinit_val => "1000000000000000",
         c_has_sset => 0,
         c_has_sinit => 0,
         c_has_q => 1,
         c_shift_type => 0,
         c_has_sdin => 1,
         c_has_lsb_2_msb => 0
      )
      PORT MAP (
         CLK => BU603_CLK,
         SDIN => BU603_SDIN,
         Q => BU603_Q,
         CE => BU603_CE
      );

   BU884_D(0) <= n87;
   BU884_D(1) <= n88;
   BU884_D(2) <= n89;
   BU884_D(3) <= n90;
   BU884_D(4) <= n91;
   BU884_D(5) <= n92;
   BU884_D(6) <= n93;
   BU884_D(7) <= n94;
   BU884_D(8) <= n95;
   BU884_D(9) <= n96;
   BU884_D(10) <= n97;
   BU884_D(11) <= n98;
   BU884_D(12) <= n99;
   BU884_D(13) <= n100;
   n2547 <= BU884_Q(0);
   n2548 <= BU884_Q(1);
   n2549 <= BU884_Q(2);
   n2550 <= BU884_Q(3);
   n2551 <= BU884_Q(4);
   n2552 <= BU884_Q(5);
   n2553 <= BU884_Q(6);
   n2554 <= BU884_Q(7);
   n2555 <= BU884_Q(8);
   n2556 <= BU884_Q(9);
   n2557 <= BU884_Q(10);
   n2558 <= BU884_Q(11);
   n2559 <= BU884_Q(12);
   n2560 <= BU884_Q(13);
   BU884_CLK <= n175;
   BU884_CE <= n176;
   BU884 : C_REG_FD_V7_0
      GENERIC MAP (
         c_width => 14,
         c_has_ce => 1,
         c_sinit_val => "00000000000000",
         c_has_sinit => 0,
         c_ainit_val => "00000000000000",
         c_has_aset => 0,
         c_sync_enable => 0,
         c_enable_rlocs => 0,
         c_has_aclr => 0,
         c_has_sset => 0,
         c_sync_priority => 0,
         c_has_ainit => 0,
         c_has_sclr => 0
      )
      PORT MAP (
         D => BU884_D,
         Q => BU884_Q,
         CLK => BU884_CLK,
         CE => BU884_CE
      );

   BU915_A(0) <= n2547;
   BU915_A(1) <= n2548;
   BU915_A(2) <= n2549;
   BU915_A(3) <= n2550;
   BU915_A(4) <= n2551;
   BU915_A(5) <= n2552;
   BU915_A(6) <= n2553;
   BU915_A(7) <= n2554;
   BU915_A(8) <= n2555;
   BU915_A(9) <= n2556;
   BU915_A(10) <= n2557;
   BU915_A(11) <= n2558;
   BU915_BYPASS <= n2559;
   BU915_CLK <= n175;
   n2587 <= BU915_Q(0);
   n2588 <= BU915_Q(1);
   n2589 <= BU915_Q(2);
   n2590 <= BU915_Q(3);
   n2591 <= BU915_Q(4);
   n2592 <= BU915_Q(5);
   n2593 <= BU915_Q(6);
   n2594 <= BU915_Q(7);
   n2595 <= BU915_Q(8);
   n2596 <= BU915_Q(9);
   n2597 <= BU915_Q(10);
   n2598 <= BU915_Q(11);
   BU915_CE <= n176;
   BU915 : C_TWOS_COMP_V7_0
      GENERIC MAP (
         c_has_aset => 0,
         c_sync_priority => 0,
         c_has_sclr => 0,
         c_width => 12,
         c_enable_rlocs => 0,
         c_has_bypass => 1,
         c_ainit_val => "0000000000000",
         c_bypass_low => 1,
         c_pipe_stages => 0,
         c_has_ce => 1,
         c_has_aclr => 0,
         c_sync_enable => 0,
         c_has_ainit => 0,
         c_sinit_val => "0000000000000",
         c_has_sset => 0,
         c_has_sinit => 0,
         c_has_s => 0,
         c_bypass_enable => 1,
         c_has_q => 1
      )
      PORT MAP (
         A => BU915_A,
         BYPASS => BU915_BYPASS,
         CLK => BU915_CLK,
         Q => BU915_Q,
         CE => BU915_CE
      );

   BU1008_CLK <= n175;
   BU1008_D(0) <= n2560;
   n2561 <= BU1008_Q(0);
   BU1008_CE <= n176;
   BU1008 : C_SHIFT_RAM_V7_0
      GENERIC MAP (
         c_has_aset => 0,
         c_read_mif => 0,
         c_has_a => 0,
         c_sync_priority => 0,
         c_has_sclr => 0,
         c_width => 1,
         c_enable_rlocs => 0,
         c_default_data_radix => 2,
         c_generate_mif => 0,
         c_ainit_val => "0",
         c_has_ce => 1,
         c_has_aclr => 0,
         c_mem_init_radix => 2,
         c_sync_enable => 0,
         c_depth => 2,
         c_has_ainit => 0,
         c_sinit_val => "0",
         c_has_sset => 0,
         c_has_sinit => 0,
         c_shift_type => 0,
         c_mem_init_file => "null",
         c_default_data => "0",
         c_reg_last_bit => 1,
         c_addr_width => 1
      )
      PORT MAP (
         CLK => BU1008_CLK,
         D => BU1008_D,
         Q => BU1008_Q,
         CE => BU1008_CE
      );

   BU1016_CLK <= n175;
   BU1016_D(0) <= n2559;
   n2562 <= BU1016_Q(0);
   BU1016_CE <= n176;
   BU1016 : C_SHIFT_RAM_V7_0
      GENERIC MAP (
         c_has_aset => 0,
         c_read_mif => 0,
         c_has_a => 0,
         c_sync_priority => 0,
         c_has_sclr => 0,
         c_width => 1,
         c_enable_rlocs => 0,
         c_default_data_radix => 2,
         c_generate_mif => 0,
         c_ainit_val => "0",
         c_has_ce => 1,
         c_has_aclr => 0,
         c_mem_init_radix => 2,
         c_sync_enable => 0,
         c_depth => 2,
         c_has_ainit => 0,
         c_sinit_val => "0",
         c_has_sset => 0,
         c_has_sinit => 0,
         c_shift_type => 0,
         c_mem_init_file => "null",
         c_default_data => "0",
         c_reg_last_bit => 1,
         c_addr_width => 1
      )
      PORT MAP (
         CLK => BU1016_CLK,
         D => BU1016_D,
         Q => BU1016_Q,
         CE => BU1016_CE
      );

   BU1027_I0 <= n2561;
   BU1027_I1 <= n2562;
   BU1027_I2 <= n2603;
   BU1027_I3 <= '0';
   n3020 <= BU1027_O;
   BU1027 : LUT4
      GENERIC MAP (
         INIT  => X"9595"
      )
      PORT MAP (
         I0 => BU1027_I0,
         I1 => BU1027_I1,
         I2 => BU1027_I2,
         I3 => BU1027_I3,
         O => BU1027_O
      );

   BU1028_D <= n3020;
   BU1028_C <= n175;
   BU1028_CE <= n176;
   BU1028_PRE <= '0';
   n2605 <= BU1028_Q;
   BU1028 : FDPE
      PORT MAP (
         D => BU1028_D,
         C => BU1028_C,
         CE => BU1028_CE,
         PRE => BU1028_PRE,
         Q => BU1028_Q
      );

   BU1032_I0 <= n2561;
   BU1032_I1 <= n2562;
   BU1032_I2 <= n2603;
   BU1032_I3 <= n2604;
   n3039 <= BU1032_O;
   BU1032 : LUT4
      GENERIC MAP (
         INIT  => X"002a"
      )
      PORT MAP (
         I0 => BU1032_I0,
         I1 => BU1032_I1,
         I2 => BU1032_I2,
         I3 => BU1032_I3,
         O => BU1032_O
      );

   BU1033_D <= n3039;
   BU1033_C <= n175;
   BU1033_CE <= n176;
   n2606 <= BU1033_Q;
   BU1033 : FDE
      PORT MAP (
         D => BU1033_D,
         C => BU1033_C,
         CE => BU1033_CE,
         Q => BU1033_Q
      );

   BU1037_I0 <= '0';
   BU1037_I1 <= n2562;
   BU1037_I2 <= n2603;
   BU1037_I3 <= '0';
   n3057 <= BU1037_O;
   BU1037 : LUT4
      GENERIC MAP (
         INIT  => X"c0c0"
      )
      PORT MAP (
         I0 => BU1037_I0,
         I1 => BU1037_I1,
         I2 => BU1037_I2,
         I3 => BU1037_I3,
         O => BU1037_O
      );

   BU1038_D <= n3057;
   BU1038_C <= n175;
   BU1038_CE <= n176;
   n2602 <= BU1038_Q;
   BU1038 : FDE
      PORT MAP (
         D => BU1038_D,
         C => BU1038_C,
         CE => BU1038_CE,
         Q => BU1038_Q
      );

   BU1040_A(0) <= n2587;
   BU1040_A(1) <= n2588;
   BU1040_A(2) <= n2589;
   BU1040_A(3) <= n2590;
   BU1040_A(4) <= n2591;
   BU1040_A(5) <= n2592;
   BU1040_A(6) <= n2593;
   BU1040_A(7) <= n2594;
   BU1040_A(8) <= n2595;
   BU1040_A(9) <= n2596;
   BU1040_A(10) <= n2597;
   BU1040_A(11) <= n2598;
   BU1040_CLK <= n175;
   BU1040_CE <= n176;
   BU1040_ACLR <= '0';
   n2604 <= BU1040_QA_GE_B;
   BU1040 : C_COMPARE_V7_0
      GENERIC MAP (
         c_has_qa_ge_b => 1,
         c_has_aset => 0,
         c_has_qa_ne_b => 0,
         c_has_qa_lt_b => 0,
         c_has_a_gt_b => 0,
         c_has_a_eq_b => 0,
         c_data_type => 1,
         c_sync_priority => 0,
         c_has_sclr => 0,
         c_has_qa_gt_b => 0,
         c_width => 12,
         c_has_qa_eq_b => 0,
         c_enable_rlocs => 0,
         c_ainit_val => "0",
         c_has_a_le_b => 0,
         c_has_ce => 1,
         c_pipe_stages => 0,
         

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