ddsqam.vhd

基于FPGA的16QAM调制与解调的设计与实现源代码

         c_sync_enable => 0,
         c_has_ce => 1,
         c_has_c_in => 0
      )
      PORT MAP (
         A => BU752_A,
         B => BU752_B,
         Q => BU752_Q,
         CLK => BU752_CLK,
         CE => BU752_CE
      );

   BU691_A(0) <= n1795;
   BU691_A(1) <= n1796;
   BU691_A(2) <= n1797;
   BU691_A(3) <= n1798;
   BU691_A(4) <= n1799;
   BU691_A(5) <= n1800;
   BU691_A(6) <= n1801;
   BU691_A(7) <= n1802;
   BU691_A(8) <= n1803;
   BU691_B(0) <= n1903;
   BU691_B(1) <= n1904;
   BU691_B(2) <= n1905;
   BU691_B(3) <= n1906;
   BU691_B(4) <= n1907;
   BU691_B(5) <= n1908;
   BU691_B(6) <= n1909;
   BU691_B(7) <= n1910;
   BU691_B(8) <= n1911;
   n101 <= BU691_Q(0);
   n102 <= BU691_Q(1);
   n103 <= BU691_Q(2);
   n104 <= BU691_Q(3);
   n105 <= BU691_Q(4);
   n106 <= BU691_Q(5);
   n107 <= BU691_Q(6);
   n108 <= BU691_Q(7);
   n109 <= BU691_Q(8);
   n110 <= BU691_Q(9);
   BU691_CLK <= n175;
   BU691_CE <= n176;
   BU691 : C_ADDSUB_V7_0
      GENERIC MAP (
         c_has_bypass_with_cin => 0,
         c_a_type => 0,
         c_has_sclr => 0,
         c_has_aset => 0,
         c_has_b_out => 0,
         c_sync_priority => 0,
         c_has_s => 1,
         c_has_q => 1,
         c_bypass_enable => 0,
         c_b_constant => 0,
         c_has_ovfl => 0,
         c_high_bit => 9,
         c_latency => 1,
         c_sinit_val => "0000000000",
         c_has_bypass => 0,
         c_pipe_stages => 0,
         c_has_sset => 0,
         c_has_ainit => 0,
         c_has_a_signed => 0,
         c_has_q_c_out => 0,
         c_b_type => 0,
         c_has_add => 0,
         c_has_sinit => 0,
         c_has_b_in => 0,
         c_has_b_signed => 0,
         c_bypass_low => 0,
         c_enable_rlocs => 0,
         c_b_value => "0000000000",
         c_add_mode => 0,
         c_has_aclr => 0,
         c_out_width => 10,
         c_low_bit => 0,
         c_ainit_val => "0000000000",
         c_has_q_ovfl => 0,
         c_has_q_b_out => 0,
         c_has_c_out => 0,
         c_b_width => 9,
         c_a_width => 9,
         c_sync_enable => 0,
         c_has_ce => 1,
         c_has_c_in => 0
      )
      PORT MAP (
         A => BU691_A,
         B => BU691_B,
         Q => BU691_Q,
         CLK => BU691_CLK,
         CE => BU691_CE
      );

   BU505_A(0) <= n1694;
   BU505_A(1) <= n1695;
   BU505_A(2) <= n1696;
   BU505_A(3) <= n1697;
   BU505_A(4) <= n1698;
   BU505_A(5) <= n1699;
   BU505_A(6) <= n1700;
   BU505_A(7) <= n1701;
   BU505_B(0) <= n1744;
   BU505_B(1) <= n1745;
   BU505_B(2) <= n1746;
   BU505_B(3) <= n1747;
   BU505_B(4) <= n1748;
   BU505_B(5) <= n1749;
   BU505_B(6) <= n1750;
   BU505_B(7) <= n1751;
   n1795 <= BU505_Q(0);
   n1796 <= BU505_Q(1);
   n1797 <= BU505_Q(2);
   n1798 <= BU505_Q(3);
   n1799 <= BU505_Q(4);
   n1800 <= BU505_Q(5);
   n1801 <= BU505_Q(6);
   n1802 <= BU505_Q(7);
   n1803 <= BU505_Q(8);
   BU505_CLK <= n175;
   BU505_CE <= n176;
   BU505 : C_ADDSUB_V7_0
      GENERIC MAP (
         c_has_bypass_with_cin => 0,
         c_a_type => 0,
         c_has_sclr => 0,
         c_has_aset => 0,
         c_has_b_out => 0,
         c_sync_priority => 0,
         c_has_s => 1,
         c_has_q => 1,
         c_bypass_enable => 0,
         c_b_constant => 0,
         c_has_ovfl => 0,
         c_high_bit => 8,
         c_latency => 1,
         c_sinit_val => "000000000",
         c_has_bypass => 0,
         c_pipe_stages => 0,
         c_has_sset => 0,
         c_has_ainit => 0,
         c_has_a_signed => 0,
         c_has_q_c_out => 0,
         c_b_type => 0,
         c_has_add => 0,
         c_has_sinit => 0,
         c_has_b_in => 0,
         c_has_b_signed => 0,
         c_bypass_low => 0,
         c_enable_rlocs => 0,
         c_b_value => "000000000",
         c_add_mode => 0,
         c_has_aclr => 0,
         c_out_width => 9,
         c_low_bit => 0,
         c_ainit_val => "000000000",
         c_has_q_ovfl => 0,
         c_has_q_b_out => 0,
         c_has_c_out => 0,
         c_b_width => 8,
         c_a_width => 8,
         c_sync_enable => 0,
         c_has_ce => 1,
         c_has_c_in => 0
      )
      PORT MAP (
         A => BU505_A,
         B => BU505_B,
         Q => BU505_Q,
         CLK => BU505_CLK,
         CE => BU505_CE
      );

   BU436_I(0) <= n1703;
   BU436_I(1) <= n1704;
   BU436_I(2) <= n1705;
   BU436_I(3) <= n1701;
   BU436_T <= '0';
   BU436_EN <= '0';
   BU436_CLK <= '0';
   BU436_CE <= '0';
   BU436_ACLR <= '0';
   BU436_ASET <= '0';
   BU436_AINIT <= '0';
   BU436_SCLR <= '0';
   BU436_SSET <= '0';
   BU436_SINIT <= '0';
   n1702 <= BU436_O;
   BU436 : C_GATE_BIT_V7_0
      GENERIC MAP (
         c_has_aset => 0,
         c_gate_type => 4,
         c_sync_priority => 1,
         c_has_sclr => 0,
         c_enable_rlocs => 0,
         c_ainit_val => "0",
         c_pipe_stages => 0,
         c_has_ce => 0,
         c_has_aclr => 0,
         c_sync_enable => 0,
         c_has_ainit => 0,
         c_sinit_val => "0",
         c_has_sset => 0,
         c_has_sinit => 0,
         c_has_q => 1,
         c_has_o => 1,
         c_inputs => 4,
         c_input_inv_mask => "0000"
      )
      PORT MAP (
         I => BU436_I,
         T => BU436_T,
         EN => BU436_EN,
         Q => BU436_Q,
         CLK => BU436_CLK,
         CE => BU436_CE,
         ACLR => BU436_ACLR,
         ASET => BU436_ASET,
         AINIT => BU436_AINIT,
         SCLR => BU436_SCLR,
         SSET => BU436_SSET,
         SINIT => BU436_SINIT,
         O => BU436_O
      );

   BU441_CLK <= n175;
   BU441_SDIN <= n1702;
   n1703 <= BU441_Q(0);
   n1704 <= BU441_Q(2);
   n1705 <= BU441_Q(3);
   n1694 <= BU441_Q(5);
   n1695 <= BU441_Q(6);
   n1696 <= BU441_Q(7);
   n1697 <= BU441_Q(8);
   n1698 <= BU441_Q(9);
   n1699 <= BU441_Q(10);
   n1700 <= BU441_Q(11);
   n1701 <= BU441_Q(12);
   BU441_CE <= n176;
   BU441 : C_SHIFT_FD_V7_0
      GENERIC MAP (
         c_has_aset => 0,
         c_has_d => 0,
         c_sync_priority => 0,
         c_has_sclr => 0,
         c_fill_data => 5,
         c_width => 13,
         c_enable_rlocs => 0,
         c_ainit_val => "1000000000000",
         c_has_ce => 1,
         c_has_aclr => 0,
         c_sync_enable => 0,
         c_has_ainit => 0,
         c_has_sdout => 0,
         c_sinit_val => "1000000000000",
         c_has_sset => 0,
         c_has_sinit => 0,
         c_has_q => 1,
         c_shift_type => 0,
         c_has_sdin => 1,
         c_has_lsb_2_msb => 0
      )
      PORT MAP (
         CLK => BU441_CLK,
         SDIN => BU441_SDIN,
         Q => BU441_Q,
         CE => BU441_CE
      );

   BU470_I(0) <= n1753;
   BU470_I(1) <= n1754;
   BU470_I(2) <= n1747;
   BU470_I(3) <= n1751;
   BU470_T <= '0';
   BU470_EN <= '0';
   BU470_CLK <= '0';
   BU470_CE <= '0';
   BU470_ACLR <= '0';
   BU470_ASET <= '0';
   BU470_AINIT <= '0';
   BU470_SCLR <= '0';
   BU470_SSET <= '0';
   BU470_SINIT <= '0';
   n1752 <= BU470_O;
   BU470 : C_GATE_BIT_V7_0
      GENERIC MAP (
         c_has_aset => 0,
         c_gate_type => 4,
         c_sync_priority => 1,
         c_has_sclr => 0,
         c_enable_rlocs => 0,
         c_ainit_val => "0",
         c_pipe_stages => 0,
         c_has_ce => 0,
         c_has_aclr => 0,
         c_sync_enable => 0,
         c_has_ainit => 0,
         c_sinit_val => "0",
         c_has_sset => 0,
         c_has_sinit => 0,
         c_has_q => 1,
         c_has_o => 1,
         c_inputs => 4,
         c_input_inv_mask => "0000"
      )
      PORT MAP (
         I => BU470_I,
         T => BU470_T,
         EN => BU470_EN,
         Q => BU470_Q,
         CLK => BU470_CLK,
         CE => BU470_CE,
         ACLR => BU470_ACLR,
         ASET => BU470_ASET,
         AINIT => BU470_AINIT,
         SCLR => BU470_SCLR,
         SSET => BU470_SSET,
         SINIT => BU470_SINIT,
         O => BU470_O
      );

   BU475_CLK <= n175;
   BU475_SDIN <= n1752;
   n1753 <= BU475_Q(0);
   n1754 <= BU475_Q(5);
   n1744 <= BU475_Q(6);
   n1745 <= BU475_Q(7);
   n1746 <= BU475_Q(8);
   n1747 <= BU475_Q(9);
   n1748 <= BU475_Q(10);
   n1749 <= BU475_Q(11);
   n1750 <= BU475_Q(12);
   n1751 <= BU475_Q(13);
   BU475_CE <= n176;
   BU475 : C_SHIFT_FD_V7_0
      GENERIC MAP (
         c_has_aset => 0,
         c_has_d => 0,
         c_sync_priority => 0,
         c_has_sclr => 0,
         c_fill_data => 5,
         c_width => 14,
         c_enable_rlocs => 0,
         c_ainit_val => "10000000000000",
         c_has_ce => 1,
         c_has_aclr => 0,
         c_sync_enable => 0,
         c_has_ainit => 0,
         c_has_sdout => 0,
         c_sinit_val => "10000000000000",
         c_has_sset => 0,
         c_has_sinit => 0,
         c_has_q => 1,
         c_shift_type => 0,
         c_has_sdin => 1,
         c_has_lsb_2_msb => 0
      )
      PORT MAP (
         CLK => BU475_CLK,
         SDIN => BU475_SDIN,
         Q => BU475_Q,
         CE => BU475_CE
      );

   BU637_A(0) <= n1804;
   BU637_A(1) <= n1805;
   BU637_A(2) <= n1806;
   BU637_A(3) <= n1807;
   BU637_A(4) <= n1808;
   BU637_A(5) <= n1809;
   BU637_A(6) <= n1810;
   BU637_A(7) <= n1811;
   BU637_B(0) <= n1850;
   BU637_B(1) <= n1851;
   BU637_B(2) <= n1852;
   BU637_B(3) <= n1853;
   BU637_B(4) <= n1854;
   BU637_B(5) <= n1855;
   BU637_B(6) <= n1856;
   BU637_B(7) <= n1857;
   n1903 <= BU637_Q(0);
   n1904 <= BU637_Q(1);
   n1905 <= BU637_Q(2);
   n1906 <= BU637_Q(3);
   n1907 <= BU637_Q(4);
   n1908 <= BU637_Q(5);
   n1909 <= BU637_Q(6);
   n1910 <= BU637_Q(7);
   n1911 <= BU637_Q(8);
   BU637_CLK <= n175;
   BU637_CE <= n176;
   BU637 : C_ADDSUB_V7_0
      GENERIC MAP (
         c_has_bypass_with_cin => 0,
         c_a_type => 0,
         c_has_sclr => 0,
         c_has_aset => 0,
         c_has_b_out => 0,
         c_sync_priority => 0,
         c_has_s => 1,
         c_has_q => 1,
         c_bypass_enable => 0,
         c_b_constant => 0,
         c_has_ovfl => 0,
         c_high_bit => 8,
         c_latency => 1,
         c_sinit_val => "000000000",
         c_has_bypass => 0,
         c_pipe_stages => 0,
         c_has_sset => 0,
         c_has_ainit => 0,
         c_has_a_signed => 0,
         c_has_q_c_out => 0,
         c_b_type => 0,
         c_has_add => 0,
         c_has_sinit => 0,
         c_has_b_in => 0,
         c_has_b_signed => 0,
         c_bypass_low => 0,
         c_enable_rlocs => 0,
         c_b_value => "000000000",
         c_add_mode => 0,
         c_has_aclr => 0,
         c_out_width => 9,
         c_low_bit => 0,
         c_ainit_val => "000000000",
         c_has_q_ovfl => 0,
         c_has_q_b_out => 0,
         c_has_c_out => 0,
         c_b_width => 8,
         c_a_width => 8,
         c_sync_enable => 0,
         c_has_ce => 1,
         c_has_c_in => 0
      )
      PORT MAP (
         A => BU637_A,
         B => BU637_B,
         Q => BU637_Q,
         CLK => BU637_CLK,
         CE => BU637_CE
      );

   BU560_I(0) <= n1813;
   BU560_I(1) <= n1811;
   BU560_T <= '0';
   BU560_EN <= '0';
   BU560_CLK <= '0';
   BU560_CE <= '0';
   BU560_ACLR <= '0';
   BU560_ASET <= '0';
   BU560_AINIT <= '0';
   BU560_SCLR <= '0';
   BU560_SSET <= '0';
   BU560_SINIT <= '0';
   n1812 <= BU560_O;
   BU560 : C_GATE_BIT_V7_0
      GENERIC MAP (
         c_has_aset => 0,
         c_gate_type => 4,
         c_sync_priority => 1,
         c_has_sclr => 0,
         c_enable_rlocs => 0,
         c_ainit_val => "0",
         c_pipe_stages => 0,
         c_has_ce => 0,
         c_has_aclr => 0,
         c_sync_enable => 0,
         c_has_ainit => 0,
         c_sinit_val => "0",
         c_has_sset => 0,