ddsqam.vhd

基于FPGA的16QAM调制与解调的设计与实现源代码

         c_sinit_val => "0000000000000000000000000",
         c_has_sinit => 0,
         c_ainit_val => "0001010001111010111000011",
         c_has_aset => 0,
         c_sync_enable => 0,
         c_enable_rlocs => 0,
         c_has_aclr => 0,
         c_has_sset => 0,
         c_sync_priority => 0,
         c_has_ainit => 0,
         c_has_sclr => 0
      )
      PORT MAP (
         D => BU20_D,
         Q => BU20_Q,
         CLK => BU20_CLK,
         CE => BU20_CE
      );

   BU72_A(0) <= n36;
   BU72_A(1) <= n37;
   BU72_A(2) <= n38;
   BU72_A(3) <= n39;
   BU72_A(4) <= n40;
   BU72_A(5) <= n41;
   BU72_A(6) <= n42;
   BU72_A(7) <= n43;
   BU72_A(8) <= n44;
   BU72_A(9) <= n45;
   BU72_A(10) <= n46;
   BU72_A(11) <= n47;
   BU72_A(12) <= n48;
   BU72_A(13) <= n49;
   BU72_A(14) <= n50;
   BU72_A(15) <= n51;
   BU72_A(16) <= n52;
   BU72_A(17) <= n53;
   BU72_A(18) <= n54;
   BU72_A(19) <= n55;
   BU72_A(20) <= n56;
   BU72_A(21) <= n57;
   BU72_A(22) <= n58;
   BU72_A(23) <= n59;
   BU72_A(24) <= n60;
   BU72_B(0) <= n282;
   BU72_B(1) <= n283;
   BU72_B(2) <= n284;
   BU72_B(3) <= n285;
   BU72_B(4) <= n286;
   BU72_B(5) <= n287;
   BU72_B(6) <= n288;
   BU72_B(7) <= n289;
   BU72_B(8) <= n290;
   BU72_B(9) <= n291;
   BU72_B(10) <= n292;
   BU72_B(11) <= n293;
   BU72_B(12) <= n294;
   BU72_B(13) <= n295;
   BU72_B(14) <= n296;
   BU72_B(15) <= n297;
   BU72_B(16) <= n298;
   BU72_B(17) <= n299;
   BU72_B(18) <= n300;
   BU72_B(19) <= n301;
   BU72_B(20) <= n302;
   BU72_B(21) <= n303;
   BU72_B(22) <= n304;
   BU72_B(23) <= n305;
   BU72_B(24) <= n306;
   n36 <= BU72_Q(0);
   n37 <= BU72_Q(1);
   n38 <= BU72_Q(2);
   n39 <= BU72_Q(3);
   n40 <= BU72_Q(4);
   n41 <= BU72_Q(5);
   n42 <= BU72_Q(6);
   n43 <= BU72_Q(7);
   n44 <= BU72_Q(8);
   n45 <= BU72_Q(9);
   n46 <= BU72_Q(10);
   n47 <= BU72_Q(11);
   n48 <= BU72_Q(12);
   n49 <= BU72_Q(13);
   n50 <= BU72_Q(14);
   n51 <= BU72_Q(15);
   n52 <= BU72_Q(16);
   n53 <= BU72_Q(17);
   n54 <= BU72_Q(18);
   n55 <= BU72_Q(19);
   n56 <= BU72_Q(20);
   n57 <= BU72_Q(21);
   n58 <= BU72_Q(22);
   n59 <= BU72_Q(23);
   n60 <= BU72_Q(24);
   BU72_CLK <= n175;
   BU72_CE <= n176;
   BU72 : C_ADDSUB_V7_0
      GENERIC MAP (
         c_has_bypass_with_cin => 0,
         c_a_type => 1,
         c_has_sclr => 0,
         c_has_aset => 0,
         c_has_b_out => 0,
         c_sync_priority => 0,
         c_has_s => 1,
         c_has_q => 1,
         c_bypass_enable => 1,
         c_b_constant => 0,
         c_has_ovfl => 0,
         c_high_bit => 24,
         c_latency => 1,
         c_sinit_val => "0000000000000000000000000",
         c_has_bypass => 0,
         c_pipe_stages => 0,
         c_has_sset => 0,
         c_has_ainit => 0,
         c_has_a_signed => 0,
         c_has_q_c_out => 0,
         c_b_type => 1,
         c_has_add => 0,
         c_has_sinit => 0,
         c_has_b_in => 0,
         c_has_b_signed => 0,
         c_bypass_low => 0,
         c_enable_rlocs => 0,
         c_b_value => "0000000000000000000000000",
         c_add_mode => 0,
         c_has_aclr => 0,
         c_out_width => 25,
         c_low_bit => 0,
         c_ainit_val => "0000000000000000000000000",
         c_has_q_ovfl => 0,
         c_has_q_b_out => 0,
         c_has_c_out => 0,
         c_b_width => 25,
         c_a_width => 25,
         c_sync_enable => 0,
         c_has_ce => 1,
         c_has_c_in => 0
      )
      PORT MAP (
         A => BU72_A,
         B => BU72_B,
         Q => BU72_Q,
         CLK => BU72_CLK,
         CE => BU72_CE
      );

   BU222_CLK <= n175;
   n86 <= BU222_SDOUT;
   BU222_CE <= n176;
   BU222 : C_SHIFT_FD_V7_0
      GENERIC MAP (
         c_has_aset => 0,
         c_has_d => 0,
         c_sync_priority => 1,
         c_has_sclr => 0,
         c_fill_data => 1,
         c_width => 2,
         c_enable_rlocs => 0,
         c_ainit_val => "00",
         c_has_ce => 1,
         c_has_aclr => 0,
         c_sync_enable => 0,
         c_has_ainit => 0,
         c_has_sdout => 1,
         c_sinit_val => "00",
         c_has_sset => 0,
         c_has_sinit => 0,
         c_has_q => 0,
         c_shift_type => 1,
         c_has_sdin => 0,
         c_has_lsb_2_msb => 0
      )
      PORT MAP (
         CLK => BU222_CLK,
         SDOUT => BU222_SDOUT,
         CE => BU222_CE
      );

   BU231_D(0) <= n144;
   BU231_D(1) <= n145;
   BU231_D(2) <= n146;
   BU231_D(3) <= n147;
   BU231_D(4) <= n148;
   BU231_D(5) <= n149;
   BU231_D(6) <= n150;
   BU231_D(7) <= n151;
   BU231_D(8) <= n152;
   BU231_D(9) <= n153;
   BU231_D(10) <= n154;
   BU231_D(11) <= n155;
   BU231_D(12) <= n156;
   BU231_D(13) <= n157;
   BU231_D(14) <= n158;
   BU231_D(15) <= n159;
   BU231_D(16) <= n160;
   BU231_D(17) <= n161;
   BU231_D(18) <= n162;
   BU231_D(19) <= n163;
   BU231_D(20) <= n164;
   BU231_D(21) <= n165;
   BU231_D(22) <= n166;
   BU231_D(23) <= n167;
   BU231_D(24) <= n168;
   n878 <= BU231_Q(0);
   n879 <= BU231_Q(1);
   n880 <= BU231_Q(2);
   n881 <= BU231_Q(3);
   n882 <= BU231_Q(4);
   n883 <= BU231_Q(5);
   n884 <= BU231_Q(6);
   n885 <= BU231_Q(7);
   n886 <= BU231_Q(8);
   n887 <= BU231_Q(9);
   n888 <= BU231_Q(10);
   n889 <= BU231_Q(11);
   n890 <= BU231_Q(12);
   n891 <= BU231_Q(13);
   n892 <= BU231_Q(14);
   n893 <= BU231_Q(15);
   n894 <= BU231_Q(16);
   n895 <= BU231_Q(17);
   n896 <= BU231_Q(18);
   n897 <= BU231_Q(19);
   n898 <= BU231_Q(20);
   n899 <= BU231_Q(21);
   n900 <= BU231_Q(22);
   n901 <= BU231_Q(23);
   n902 <= BU231_Q(24);
   BU231_CLK <= n175;
   BU231_CE <= n19;
   BU231 : C_REG_FD_V7_0
      GENERIC MAP (
         c_width => 25,
         c_has_ce => 1,
         c_sinit_val => "0000000000000000000000000",
         c_has_sinit => 0,
         c_ainit_val => "0000000000000000000000000",
         c_has_aset => 0,
         c_sync_enable => 0,
         c_enable_rlocs => 0,
         c_has_aclr => 0,
         c_has_sset => 0,
         c_sync_priority => 0,
         c_has_ainit => 0,
         c_has_sclr => 0
      )
      PORT MAP (
         D => BU231_D,
         Q => BU231_Q,
         CLK => BU231_CLK,
         CE => BU231_CE
      );

   BU283_A(0) <= n36;
   BU283_A(1) <= n37;
   BU283_A(2) <= n38;
   BU283_A(3) <= n39;
   BU283_A(4) <= n40;
   BU283_A(5) <= n41;
   BU283_A(6) <= n42;
   BU283_A(7) <= n43;
   BU283_A(8) <= n44;
   BU283_A(9) <= n45;
   BU283_A(10) <= n46;
   BU283_A(11) <= n47;
   BU283_A(12) <= n48;
   BU283_A(13) <= n49;
   BU283_A(14) <= n50;
   BU283_A(15) <= n51;
   BU283_A(16) <= n52;
   BU283_A(17) <= n53;
   BU283_A(18) <= n54;
   BU283_A(19) <= n55;
   BU283_A(20) <= n56;
   BU283_A(21) <= n57;
   BU283_A(22) <= n58;
   BU283_A(23) <= n59;
   BU283_A(24) <= n60;
   BU283_B(0) <= n878;
   BU283_B(1) <= n879;
   BU283_B(2) <= n880;
   BU283_B(3) <= n881;
   BU283_B(4) <= n882;
   BU283_B(5) <= n883;
   BU283_B(6) <= n884;
   BU283_B(7) <= n885;
   BU283_B(8) <= n886;
   BU283_B(9) <= n887;
   BU283_B(10) <= n888;
   BU283_B(11) <= n889;
   BU283_B(12) <= n890;
   BU283_B(13) <= n891;
   BU283_B(14) <= n892;
   BU283_B(15) <= n893;
   BU283_B(16) <= n894;
   BU283_B(17) <= n895;
   BU283_B(18) <= n896;
   BU283_B(19) <= n897;
   BU283_B(20) <= n898;
   BU283_B(21) <= n899;
   BU283_B(22) <= n900;
   BU283_B(23) <= n901;
   BU283_B(24) <= n902;
   n63 <= BU283_Q(2);
   n64 <= BU283_Q(3);
   n65 <= BU283_Q(4);
   n66 <= BU283_Q(5);
   n67 <= BU283_Q(6);
   n68 <= BU283_Q(7);
   n69 <= BU283_Q(8);
   n70 <= BU283_Q(9);
   n71 <= BU283_Q(10);
   n72 <= BU283_Q(11);
   n73 <= BU283_Q(12);
   n74 <= BU283_Q(13);
   n75 <= BU283_Q(14);
   n76 <= BU283_Q(15);
   n77 <= BU283_Q(16);
   n78 <= BU283_Q(17);
   n79 <= BU283_Q(18);
   n80 <= BU283_Q(19);
   n81 <= BU283_Q(20);
   n82 <= BU283_Q(21);
   n83 <= BU283_Q(22);
   n84 <= BU283_Q(23);
   n85 <= BU283_Q(24);
   BU283_CLK <= n175;
   BU283_CE <= n176;
   BU283 : C_ADDSUB_V7_0
      GENERIC MAP (
         c_has_bypass_with_cin => 0,
         c_a_type => 1,
         c_has_sclr => 0,
         c_has_aset => 0,
         c_has_b_out => 0,
         c_sync_priority => 0,
         c_has_s => 1,
         c_has_q => 1,
         c_bypass_enable => 1,
         c_b_constant => 0,
         c_has_ovfl => 0,
         c_high_bit => 24,
         c_latency => 1,
         c_sinit_val => "0000000000000000000000000",
         c_has_bypass => 0,
         c_pipe_stages => 0,
         c_has_sset => 0,
         c_has_ainit => 0,
         c_has_a_signed => 0,
         c_has_q_c_out => 0,
         c_b_type => 1,
         c_has_add => 0,
         c_has_sinit => 0,
         c_has_b_in => 0,
         c_has_b_signed => 0,
         c_bypass_low => 0,
         c_enable_rlocs => 0,
         c_b_value => "0000000000000000000000000",
         c_add_mode => 0,
         c_has_aclr => 0,
         c_out_width => 25,
         c_low_bit => 0,
         c_ainit_val => "0000000000000000000000000",
         c_has_q_ovfl => 0,
         c_has_q_b_out => 0,
         c_has_c_out => 0,
         c_b_width => 25,
         c_a_width => 25,
         c_sync_enable => 0,
         c_has_ce => 1,
         c_has_c_in => 0
      )
      PORT MAP (
         A => BU283_A,
         B => BU283_B,
         Q => BU283_Q,
         CLK => BU283_CLK,
         CE => BU283_CE
      );

   BU752_A(0) <= n63;
   BU752_A(1) <= n64;
   BU752_A(2) <= n65;
   BU752_A(3) <= n66;
   BU752_A(4) <= n67;
   BU752_A(5) <= n68;
   BU752_A(6) <= n69;
   BU752_A(7) <= n70;
   BU752_A(8) <= n71;
   BU752_A(9) <= n72;
   BU752_A(10) <= n73;
   BU752_A(11) <= n74;
   BU752_A(12) <= n75;
   BU752_A(13) <= n76;
   BU752_A(14) <= n77;
   BU752_A(15) <= n78;
   BU752_A(16) <= n79;
   BU752_A(17) <= n80;
   BU752_A(18) <= n81;
   BU752_A(19) <= n82;
   BU752_A(20) <= n83;
   BU752_A(21) <= n84;
   BU752_A(22) <= n85;
   BU752_B(0) <= n101;
   BU752_B(1) <= n102;
   BU752_B(2) <= n103;
   BU752_B(3) <= n104;
   BU752_B(4) <= n105;
   BU752_B(5) <= n106;
   BU752_B(6) <= n107;
   BU752_B(7) <= n108;
   BU752_B(8) <= n109;
   BU752_B(9) <= n110;
   n87 <= BU752_Q(0);
   n88 <= BU752_Q(1);
   n89 <= BU752_Q(2);
   n90 <= BU752_Q(3);
   n91 <= BU752_Q(4);
   n92 <= BU752_Q(5);
   n93 <= BU752_Q(6);
   n94 <= BU752_Q(7);
   n95 <= BU752_Q(8);
   n96 <= BU752_Q(9);
   n97 <= BU752_Q(10);
   n98 <= BU752_Q(11);
   n99 <= BU752_Q(12);
   n100 <= BU752_Q(13);
   BU752_CLK <= n175;
   BU752_CE <= n176;
   BU752 : C_ADDSUB_V7_0
      GENERIC MAP (
         c_has_bypass_with_cin => 0,
         c_a_type => 1,
         c_has_sclr => 0,
         c_has_aset => 0,
         c_has_b_out => 0,
         c_sync_priority => 0,
         c_has_s => 1,
         c_has_q => 1,
         c_bypass_enable => 1,
         c_b_constant => 0,
         c_has_ovfl => 0,
         c_high_bit => 22,
         c_latency => 1,
         c_sinit_val => "00000000000000",
         c_has_bypass => 0,
         c_pipe_stages => 0,
         c_has_sset => 0,
         c_has_ainit => 0,
         c_has_a_signed => 0,
         c_has_q_c_out => 0,
         c_b_type => 0,
         c_has_add => 0,
         c_has_sinit => 0,
         c_has_b_in => 0,
         c_has_b_signed => 0,
         c_bypass_low => 0,
         c_enable_rlocs => 0,
         c_b_value => "00000000000000000000000",
         c_add_mode => 0,
         c_has_aclr => 0,
         c_out_width => 14,
         c_low_bit => 9,
         c_ainit_val => "00000000000000",
         c_has_q_ovfl => 0,
         c_has_q_b_out => 0,
         c_has_c_out => 0,
         c_b_width => 10,
         c_a_width => 23,