ddsqam.vhd

基于FPGA的16QAM调制与解调的设计与实现源代码

   SIGNAL n187 : STD_LOGIC;
   SIGNAL n188 : STD_LOGIC;
   SIGNAL n189 : STD_LOGIC;
   SIGNAL n190 : STD_LOGIC;
   SIGNAL n191 : STD_LOGIC;
   SIGNAL n192 : STD_LOGIC;
   SIGNAL n193 : STD_LOGIC;
   SIGNAL n194 : STD_LOGIC;
   SIGNAL n195 : STD_LOGIC;
   SIGNAL n196 : STD_LOGIC;
   SIGNAL n197 : STD_LOGIC;
   SIGNAL n198 : STD_LOGIC;
   SIGNAL n199 : STD_LOGIC;
   SIGNAL n200 : STD_LOGIC;
   SIGNAL n201 : STD_LOGIC;
   SIGNAL n202 : STD_LOGIC;
   SIGNAL n203 : STD_LOGIC;
   SIGNAL n204 : STD_LOGIC;
   SIGNAL n205 : STD_LOGIC;
   SIGNAL n206 : STD_LOGIC;
   SIGNAL n207 : STD_LOGIC;
   SIGNAL n208 : STD_LOGIC;
   SIGNAL n282 : STD_LOGIC;
   SIGNAL n283 : STD_LOGIC;
   SIGNAL n284 : STD_LOGIC;
   SIGNAL n285 : STD_LOGIC;
   SIGNAL n286 : STD_LOGIC;
   SIGNAL n287 : STD_LOGIC;
   SIGNAL n288 : STD_LOGIC;
   SIGNAL n289 : STD_LOGIC;
   SIGNAL n290 : STD_LOGIC;
   SIGNAL n291 : STD_LOGIC;
   SIGNAL n292 : STD_LOGIC;
   SIGNAL n293 : STD_LOGIC;
   SIGNAL n294 : STD_LOGIC;
   SIGNAL n295 : STD_LOGIC;
   SIGNAL n296 : STD_LOGIC;
   SIGNAL n297 : STD_LOGIC;
   SIGNAL n298 : STD_LOGIC;
   SIGNAL n299 : STD_LOGIC;
   SIGNAL n300 : STD_LOGIC;
   SIGNAL n301 : STD_LOGIC;
   SIGNAL n302 : STD_LOGIC;
   SIGNAL n303 : STD_LOGIC;
   SIGNAL n304 : STD_LOGIC;
   SIGNAL n305 : STD_LOGIC;
   SIGNAL n306 : STD_LOGIC;
   SIGNAL n878 : STD_LOGIC;
   SIGNAL n879 : STD_LOGIC;
   SIGNAL n880 : STD_LOGIC;
   SIGNAL n881 : STD_LOGIC;
   SIGNAL n882 : STD_LOGIC;
   SIGNAL n883 : STD_LOGIC;
   SIGNAL n884 : STD_LOGIC;
   SIGNAL n885 : STD_LOGIC;
   SIGNAL n886 : STD_LOGIC;
   SIGNAL n887 : STD_LOGIC;
   SIGNAL n888 : STD_LOGIC;
   SIGNAL n889 : STD_LOGIC;
   SIGNAL n890 : STD_LOGIC;
   SIGNAL n891 : STD_LOGIC;
   SIGNAL n892 : STD_LOGIC;
   SIGNAL n893 : STD_LOGIC;
   SIGNAL n894 : STD_LOGIC;
   SIGNAL n895 : STD_LOGIC;
   SIGNAL n896 : STD_LOGIC;
   SIGNAL n897 : STD_LOGIC;
   SIGNAL n898 : STD_LOGIC;
   SIGNAL n899 : STD_LOGIC;
   SIGNAL n900 : STD_LOGIC;
   SIGNAL n901 : STD_LOGIC;
   SIGNAL n902 : STD_LOGIC;
   SIGNAL n1694 : STD_LOGIC;
   SIGNAL n1695 : STD_LOGIC;
   SIGNAL n1696 : STD_LOGIC;
   SIGNAL n1697 : STD_LOGIC;
   SIGNAL n1698 : STD_LOGIC;
   SIGNAL n1699 : STD_LOGIC;
   SIGNAL n1700 : STD_LOGIC;
   SIGNAL n1701 : STD_LOGIC;
   SIGNAL n1702 : STD_LOGIC;
   SIGNAL n1703 : STD_LOGIC;
   SIGNAL n1704 : STD_LOGIC;
   SIGNAL n1705 : STD_LOGIC;
   SIGNAL n1744 : STD_LOGIC;
   SIGNAL n1745 : STD_LOGIC;
   SIGNAL n1746 : STD_LOGIC;
   SIGNAL n1747 : STD_LOGIC;
   SIGNAL n1748 : STD_LOGIC;
   SIGNAL n1749 : STD_LOGIC;
   SIGNAL n1750 : STD_LOGIC;
   SIGNAL n1751 : STD_LOGIC;
   SIGNAL n1752 : STD_LOGIC;
   SIGNAL n1753 : STD_LOGIC;
   SIGNAL n1754 : STD_LOGIC;
   SIGNAL n1795 : STD_LOGIC;
   SIGNAL n1796 : STD_LOGIC;
   SIGNAL n1797 : STD_LOGIC;
   SIGNAL n1798 : STD_LOGIC;
   SIGNAL n1799 : STD_LOGIC;
   SIGNAL n1800 : STD_LOGIC;
   SIGNAL n1801 : STD_LOGIC;
   SIGNAL n1802 : STD_LOGIC;
   SIGNAL n1803 : STD_LOGIC;
   SIGNAL n1804 : STD_LOGIC;
   SIGNAL n1805 : STD_LOGIC;
   SIGNAL n1806 : STD_LOGIC;
   SIGNAL n1807 : STD_LOGIC;
   SIGNAL n1808 : STD_LOGIC;
   SIGNAL n1809 : STD_LOGIC;
   SIGNAL n1810 : STD_LOGIC;
   SIGNAL n1811 : STD_LOGIC;
   SIGNAL n1812 : STD_LOGIC;
   SIGNAL n1813 : STD_LOGIC;
   SIGNAL n1850 : STD_LOGIC;
   SIGNAL n1851 : STD_LOGIC;
   SIGNAL n1852 : STD_LOGIC;
   SIGNAL n1853 : STD_LOGIC;
   SIGNAL n1854 : STD_LOGIC;
   SIGNAL n1855 : STD_LOGIC;
   SIGNAL n1856 : STD_LOGIC;
   SIGNAL n1857 : STD_LOGIC;
   SIGNAL n1858 : STD_LOGIC;
   SIGNAL n1859 : STD_LOGIC;
   SIGNAL n1860 : STD_LOGIC;
   SIGNAL n1903 : STD_LOGIC;
   SIGNAL n1904 : STD_LOGIC;
   SIGNAL n1905 : STD_LOGIC;
   SIGNAL n1906 : STD_LOGIC;
   SIGNAL n1907 : STD_LOGIC;
   SIGNAL n1908 : STD_LOGIC;
   SIGNAL n1909 : STD_LOGIC;
   SIGNAL n1910 : STD_LOGIC;
   SIGNAL n1911 : STD_LOGIC;
   SIGNAL n2547 : STD_LOGIC;
   SIGNAL n2548 : STD_LOGIC;
   SIGNAL n2549 : STD_LOGIC;
   SIGNAL n2550 : STD_LOGIC;
   SIGNAL n2551 : STD_LOGIC;
   SIGNAL n2552 : STD_LOGIC;
   SIGNAL n2553 : STD_LOGIC;
   SIGNAL n2554 : STD_LOGIC;
   SIGNAL n2555 : STD_LOGIC;
   SIGNAL n2556 : STD_LOGIC;
   SIGNAL n2557 : STD_LOGIC;
   SIGNAL n2558 : STD_LOGIC;
   SIGNAL n2559 : STD_LOGIC;
   SIGNAL n2560 : STD_LOGIC;
   SIGNAL n2561 : STD_LOGIC;
   SIGNAL n2562 : STD_LOGIC;
   SIGNAL n2587 : STD_LOGIC;
   SIGNAL n2588 : STD_LOGIC;
   SIGNAL n2589 : STD_LOGIC;
   SIGNAL n2590 : STD_LOGIC;
   SIGNAL n2591 : STD_LOGIC;
   SIGNAL n2592 : STD_LOGIC;
   SIGNAL n2593 : STD_LOGIC;
   SIGNAL n2594 : STD_LOGIC;
   SIGNAL n2595 : STD_LOGIC;
   SIGNAL n2596 : STD_LOGIC;
   SIGNAL n2597 : STD_LOGIC;
   SIGNAL n2598 : STD_LOGIC;
   SIGNAL n2602 : STD_LOGIC;
   SIGNAL n2603 : STD_LOGIC;
   SIGNAL n2604 : STD_LOGIC;
   SIGNAL n2605 : STD_LOGIC;
   SIGNAL n2606 : STD_LOGIC;
   SIGNAL n2607 : STD_LOGIC;
   SIGNAL n2608 : STD_LOGIC;
   SIGNAL n2609 : STD_LOGIC;
   SIGNAL n2610 : STD_LOGIC;
   SIGNAL n2611 : STD_LOGIC;
   SIGNAL n2612 : STD_LOGIC;
   SIGNAL n2613 : STD_LOGIC;
   SIGNAL n2614 : STD_LOGIC;
   SIGNAL n2615 : STD_LOGIC;
   SIGNAL n2616 : STD_LOGIC;
   SIGNAL n2617 : STD_LOGIC;
   SIGNAL n2618 : STD_LOGIC;
   SIGNAL n2619 : STD_LOGIC;
   SIGNAL n2620 : STD_LOGIC;
   SIGNAL n2621 : STD_LOGIC;
   SIGNAL n2638 : STD_LOGIC;
   SIGNAL n2639 : STD_LOGIC;
   SIGNAL n2640 : STD_LOGIC;
   SIGNAL n2641 : STD_LOGIC;
   SIGNAL n2642 : STD_LOGIC;
   SIGNAL n2643 : STD_LOGIC;
   SIGNAL n2644 : STD_LOGIC;
   SIGNAL n2645 : STD_LOGIC;
   SIGNAL n2646 : STD_LOGIC;
   SIGNAL n2647 : STD_LOGIC;
   SIGNAL n2648 : STD_LOGIC;
   SIGNAL n2649 : STD_LOGIC;
   SIGNAL n2650 : STD_LOGIC;
   SIGNAL n2651 : STD_LOGIC;
   SIGNAL n2652 : STD_LOGIC;
   SIGNAL n2653 : STD_LOGIC;
   SIGNAL n2678 : STD_LOGIC;
   SIGNAL n2679 : STD_LOGIC;
   SIGNAL n2680 : STD_LOGIC;
   SIGNAL n2681 : STD_LOGIC;
   SIGNAL n2682 : STD_LOGIC;
   SIGNAL n2683 : STD_LOGIC;
   SIGNAL n2684 : STD_LOGIC;
   SIGNAL n2685 : STD_LOGIC;
   SIGNAL n2686 : STD_LOGIC;
   SIGNAL n2687 : STD_LOGIC;
   SIGNAL n2688 : STD_LOGIC;
   SIGNAL n2689 : STD_LOGIC;
   SIGNAL n2693 : STD_LOGIC;
   SIGNAL n2694 : STD_LOGIC;
   SIGNAL n2695 : STD_LOGIC;
   SIGNAL n2696 : STD_LOGIC;
   SIGNAL n2697 : STD_LOGIC;
   SIGNAL n2698 : STD_LOGIC;
   SIGNAL n2699 : STD_LOGIC;
   SIGNAL n2700 : STD_LOGIC;
   SIGNAL n2701 : STD_LOGIC;
   SIGNAL n2702 : STD_LOGIC;
   SIGNAL n2703 : STD_LOGIC;
   SIGNAL n2704 : STD_LOGIC;
   SIGNAL n2705 : STD_LOGIC;
   SIGNAL n2706 : STD_LOGIC;
   SIGNAL n2707 : STD_LOGIC;
   SIGNAL n2708 : STD_LOGIC;
   SIGNAL n2709 : STD_LOGIC;
   SIGNAL n2710 : STD_LOGIC;
   SIGNAL n2711 : STD_LOGIC;
   SIGNAL n2712 : STD_LOGIC;
   SIGNAL n2729 : STD_LOGIC;
   SIGNAL n2747 : STD_LOGIC;
   SIGNAL n3020 : STD_LOGIC;
   SIGNAL n3039 : STD_LOGIC;
   SIGNAL n3057 : STD_LOGIC;
   SIGNAL n3339 : STD_LOGIC;
   SIGNAL n3358 : STD_LOGIC;
   SIGNAL n3376 : STD_LOGIC;

BEGIN

   n144 <= DATA(0);
   n145 <= DATA(1);
   n146 <= DATA(2);
   n147 <= DATA(3);
   n148 <= DATA(4);
   n149 <= DATA(5);
   n150 <= DATA(6);
   n151 <= DATA(7);
   n152 <= DATA(8);
   n153 <= DATA(9);
   n154 <= DATA(10);
   n155 <= DATA(11);
   n156 <= DATA(12);
   n157 <= DATA(13);
   n158 <= DATA(14);
   n159 <= DATA(15);
   n160 <= DATA(16);
   n161 <= DATA(17);
   n162 <= DATA(18);
   n163 <= DATA(19);
   n164 <= DATA(20);
   n165 <= DATA(21);
   n166 <= DATA(22);
   n167 <= DATA(23);
   n168 <= DATA(24);
   n25 <= WE;
   n20 <= A(0);
   n21 <= A(1);
   n22 <= A(2);
   n23 <= A(3);
   n24 <= A(4);
   n175 <= CLK;
   n176 <= CE;
   SINE(0) <= n177;
   SINE(1) <= n178;
   SINE(2) <= n179;
   SINE(3) <= n180;
   SINE(4) <= n181;
   SINE(5) <= n182;
   SINE(6) <= n183;
   SINE(7) <= n184;
   SINE(8) <= n185;
   SINE(9) <= n186;
   SINE(10) <= n187;
   SINE(11) <= n188;
   SINE(12) <= n189;
   SINE(13) <= n190;
   SINE(14) <= n191;
   SINE(15) <= n192;
   COSINE(0) <= n193;
   COSINE(1) <= n194;
   COSINE(2) <= n195;
   COSINE(3) <= n196;
   COSINE(4) <= n197;
   COSINE(5) <= n198;
   COSINE(6) <= n199;
   COSINE(7) <= n200;
   COSINE(8) <= n201;
   COSINE(9) <= n202;
   COSINE(10) <= n203;
   COSINE(11) <= n204;
   COSINE(12) <= n205;
   COSINE(13) <= n206;
   COSINE(14) <= n207;
   COSINE(15) <= n208;

   BU2_I(0) <= n20;
   BU2_I(1) <= n21;
   BU2_I(2) <= n22;
   BU2_I(3) <= n23;
   BU2_I(4) <= n24;
   BU2_I(5) <= n25;
   BU2_T <= '0';
   BU2_EN <= '0';
   BU2_CLK <= '0';
   BU2_CE <= '0';
   BU2_ACLR <= '0';
   BU2_ASET <= '0';
   BU2_AINIT <= '0';
   BU2_SCLR <= '0';
   BU2_SSET <= '0';
   BU2_SINIT <= '0';
   n2 <= BU2_O;
   BU2 : C_GATE_BIT_V7_0
      GENERIC MAP (
         c_has_aset => 0,
         c_gate_type => 0,
         c_sync_priority => 1,
         c_has_sclr => 0,
         c_enable_rlocs => 0,
         c_ainit_val => "0",
         c_pipe_stages => 0,
         c_has_ce => 0,
         c_has_aclr => 0,
         c_sync_enable => 0,
         c_has_ainit => 0,
         c_sinit_val => "0",
         c_has_sset => 0,
         c_has_sinit => 0,
         c_has_q => 1,
         c_has_o => 1,
         c_inputs => 6,
         c_input_inv_mask => "011111"
      )
      PORT MAP (
         I => BU2_I,
         T => BU2_T,
         EN => BU2_EN,
         Q => BU2_Q,
         CLK => BU2_CLK,
         CE => BU2_CE,
         ACLR => BU2_ACLR,
         ASET => BU2_ASET,
         AINIT => BU2_AINIT,
         SCLR => BU2_SCLR,
         SSET => BU2_SSET,
         SINIT => BU2_SINIT,
         O => BU2_O
      );

   BU10_I(0) <= n20;
   BU10_I(1) <= n21;
   BU10_I(2) <= n22;
   BU10_I(3) <= n23;
   BU10_I(4) <= n24;
   BU10_I(5) <= n25;
   BU10_T <= '0';
   BU10_EN <= '0';
   BU10_CLK <= '0';
   BU10_CE <= '0';
   BU10_ACLR <= '0';
   BU10_ASET <= '0';
   BU10_AINIT <= '0';
   BU10_SCLR <= '0';
   BU10_SSET <= '0';
   BU10_SINIT <= '0';
   n19 <= BU10_O;
   BU10 : C_GATE_BIT_V7_0
      GENERIC MAP (
         c_has_aset => 0,
         c_gate_type => 0,
         c_sync_priority => 1,
         c_has_sclr => 0,
         c_enable_rlocs => 0,
         c_ainit_val => "0",
         c_pipe_stages => 0,
         c_has_ce => 0,
         c_has_aclr => 0,
         c_sync_enable => 0,
         c_has_ainit => 0,
         c_sinit_val => "0",
         c_has_sset => 0,
         c_has_sinit => 0,
         c_has_q => 1,
         c_has_o => 1,
         c_inputs => 6,
         c_input_inv_mask => "001111"
      )
      PORT MAP (
         I => BU10_I,
         T => BU10_T,
         EN => BU10_EN,
         Q => BU10_Q,
         CLK => BU10_CLK,
         CE => BU10_CE,
         ACLR => BU10_ACLR,
         ASET => BU10_ASET,
         AINIT => BU10_AINIT,
         SCLR => BU10_SCLR,
         SSET => BU10_SSET,
         SINIT => BU10_SINIT,
         O => BU10_O
      );

   BU20_D(0) <= n144;
   BU20_D(1) <= n145;
   BU20_D(2) <= n146;
   BU20_D(3) <= n147;
   BU20_D(4) <= n148;
   BU20_D(5) <= n149;
   BU20_D(6) <= n150;
   BU20_D(7) <= n151;
   BU20_D(8) <= n152;
   BU20_D(9) <= n153;
   BU20_D(10) <= n154;
   BU20_D(11) <= n155;
   BU20_D(12) <= n156;
   BU20_D(13) <= n157;
   BU20_D(14) <= n158;
   BU20_D(15) <= n159;
   BU20_D(16) <= n160;
   BU20_D(17) <= n161;
   BU20_D(18) <= n162;
   BU20_D(19) <= n163;
   BU20_D(20) <= n164;
   BU20_D(21) <= n165;
   BU20_D(22) <= n166;
   BU20_D(23) <= n167;
   BU20_D(24) <= n168;
   n282 <= BU20_Q(0);
   n283 <= BU20_Q(1);
   n284 <= BU20_Q(2);
   n285 <= BU20_Q(3);
   n286 <= BU20_Q(4);
   n287 <= BU20_Q(5);
   n288 <= BU20_Q(6);
   n289 <= BU20_Q(7);
   n290 <= BU20_Q(8);
   n291 <= BU20_Q(9);
   n292 <= BU20_Q(10);
   n293 <= BU20_Q(11);
   n294 <= BU20_Q(12);
   n295 <= BU20_Q(13);
   n296 <= BU20_Q(14);
   n297 <= BU20_Q(15);
   n298 <= BU20_Q(16);
   n299 <= BU20_Q(17);
   n300 <= BU20_Q(18);
   n301 <= BU20_Q(19);
   n302 <= BU20_Q(20);
   n303 <= BU20_Q(21);
   n304 <= BU20_Q(22);
   n305 <= BU20_Q(23);
   n306 <= BU20_Q(24);
   BU20_CLK <= n175;
   BU20_CE <= n2;
   BU20 : C_REG_FD_V7_0
      GENERIC MAP (
         c_width => 25,
         c_has_ce => 1,