ddsqam.vhd

基于FPGA的16QAM调制与解调的设计与实现源代码

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--     This file is owned and controlled by Xilinx and must be used           --
--     solely for design, simulation, implementation and creation of          --
--     design files limited to Xilinx devices or technologies. Use            --
--     with non-Xilinx devices or technologies is expressly prohibited        --
--     and immediately terminates your license.                               --
--                                                                            --
--     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"          --
--     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                --
--     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION        --
--     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION            --
--     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS              --
--     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                --
--     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE       --
--     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY               --
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--     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF        --
--     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS        --
--     FOR A PARTICULAR PURPOSE.                                              --
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--     Xilinx products are not intended for use in life support               --
--     appliances, devices, or systems. Use in such applications are          --
--     expressly prohibited.                                                  --
--                                                                            --
--     (c) Copyright 1995-2007 Xilinx, Inc.                                   --
--     All rights reserved.                                                   --
--------------------------------------------------------------------------------

-- synthesis translate_off
LIBRARY std, ieee;
USE std.standard.ALL;
USE ieee.std_logic_1164.ALL;

LIBRARY unisim;
USE unisim.vcomponents.ALL;


LIBRARY XilinxCoreLib;
USE XilinxCoreLib.c_compare_v7_0_comp.ALL;
USE XilinxCoreLib.c_shift_ram_v7_0_comp.ALL;
USE XilinxCoreLib.c_reg_fd_v7_0_comp.ALL;
USE XilinxCoreLib.blkmemdp_v6_0_comp.ALL;
USE XilinxCoreLib.c_twos_comp_v7_0_comp.ALL;
USE XilinxCoreLib.c_gate_bit_v7_0_comp.ALL;
USE XilinxCoreLib.c_shift_fd_v7_0_comp.ALL;
USE XilinxCoreLib.c_addsub_v7_0_comp.ALL;

ENTITY ddsqam IS
   PORT (
      DATA : IN STD_LOGIC_VECTOR(24 DOWNTO 0);
      WE : IN STD_LOGIC;
      A : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
      CLK : IN STD_LOGIC;
      CE : IN STD_LOGIC;
      SINE : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
      COSINE : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)   
);
END ddsqam;

ARCHITECTURE xilinx OF ddsqam IS 

-- Signals for connecting to instantiations
   SIGNAL BU2_I : STD_LOGIC_VECTOR(5 DOWNTO 0);
   SIGNAL BU2_T : STD_LOGIC;
   SIGNAL BU2_EN : STD_LOGIC;
   SIGNAL BU2_Q : STD_LOGIC;
   SIGNAL BU2_CLK : STD_LOGIC;
   SIGNAL BU2_CE : STD_LOGIC;
   SIGNAL BU2_ACLR : STD_LOGIC;
   SIGNAL BU2_ASET : STD_LOGIC;
   SIGNAL BU2_AINIT : STD_LOGIC;
   SIGNAL BU2_SCLR : STD_LOGIC;
   SIGNAL BU2_SSET : STD_LOGIC;
   SIGNAL BU2_SINIT : STD_LOGIC;
   SIGNAL BU2_O : STD_LOGIC;
   SIGNAL BU10_I : STD_LOGIC_VECTOR(5 DOWNTO 0);
   SIGNAL BU10_T : STD_LOGIC;
   SIGNAL BU10_EN : STD_LOGIC;
   SIGNAL BU10_Q : STD_LOGIC;
   SIGNAL BU10_CLK : STD_LOGIC;
   SIGNAL BU10_CE : STD_LOGIC;
   SIGNAL BU10_ACLR : STD_LOGIC;
   SIGNAL BU10_ASET : STD_LOGIC;
   SIGNAL BU10_AINIT : STD_LOGIC;
   SIGNAL BU10_SCLR : STD_LOGIC;
   SIGNAL BU10_SSET : STD_LOGIC;
   SIGNAL BU10_SINIT : STD_LOGIC;
   SIGNAL BU10_O : STD_LOGIC;
   SIGNAL BU20_D : STD_LOGIC_VECTOR(24 DOWNTO 0);
   SIGNAL BU20_Q : STD_LOGIC_VECTOR(24 DOWNTO 0);
   SIGNAL BU20_CLK : STD_LOGIC;
   SIGNAL BU20_CE : STD_LOGIC;
   SIGNAL BU72_A : STD_LOGIC_VECTOR(24 DOWNTO 0);
   SIGNAL BU72_B : STD_LOGIC_VECTOR(24 DOWNTO 0);
   SIGNAL BU72_Q : STD_LOGIC_VECTOR(24 DOWNTO 0);
   SIGNAL BU72_CLK : STD_LOGIC;
   SIGNAL BU72_CE : STD_LOGIC;
   SIGNAL BU222_CLK : STD_LOGIC;
   SIGNAL BU222_SDOUT : STD_LOGIC;
   SIGNAL BU222_CE : STD_LOGIC;
   SIGNAL BU231_D : STD_LOGIC_VECTOR(24 DOWNTO 0);
   SIGNAL BU231_Q : STD_LOGIC_VECTOR(24 DOWNTO 0);
   SIGNAL BU231_CLK : STD_LOGIC;
   SIGNAL BU231_CE : STD_LOGIC;
   SIGNAL BU283_A : STD_LOGIC_VECTOR(24 DOWNTO 0);
   SIGNAL BU283_B : STD_LOGIC_VECTOR(24 DOWNTO 0);
   SIGNAL BU283_Q : STD_LOGIC_VECTOR(24 DOWNTO 0);
   SIGNAL BU283_CLK : STD_LOGIC;
   SIGNAL BU283_CE : STD_LOGIC;
   SIGNAL BU752_A : STD_LOGIC_VECTOR(22 DOWNTO 0);
   SIGNAL BU752_B : STD_LOGIC_VECTOR(9 DOWNTO 0);
   SIGNAL BU752_Q : STD_LOGIC_VECTOR(13 DOWNTO 0);
   SIGNAL BU752_CLK : STD_LOGIC;
   SIGNAL BU752_CE : STD_LOGIC;
   SIGNAL BU691_A : STD_LOGIC_VECTOR(8 DOWNTO 0);
   SIGNAL BU691_B : STD_LOGIC_VECTOR(8 DOWNTO 0);
   SIGNAL BU691_Q : STD_LOGIC_VECTOR(9 DOWNTO 0);
   SIGNAL BU691_CLK : STD_LOGIC;
   SIGNAL BU691_CE : STD_LOGIC;
   SIGNAL BU505_A : STD_LOGIC_VECTOR(7 DOWNTO 0);
   SIGNAL BU505_B : STD_LOGIC_VECTOR(7 DOWNTO 0);
   SIGNAL BU505_Q : STD_LOGIC_VECTOR(8 DOWNTO 0);
   SIGNAL BU505_CLK : STD_LOGIC;
   SIGNAL BU505_CE : STD_LOGIC;
   SIGNAL BU436_I : STD_LOGIC_VECTOR(3 DOWNTO 0);
   SIGNAL BU436_T : STD_LOGIC;
   SIGNAL BU436_EN : STD_LOGIC;
   SIGNAL BU436_Q : STD_LOGIC;
   SIGNAL BU436_CLK : STD_LOGIC;
   SIGNAL BU436_CE : STD_LOGIC;
   SIGNAL BU436_ACLR : STD_LOGIC;
   SIGNAL BU436_ASET : STD_LOGIC;
   SIGNAL BU436_AINIT : STD_LOGIC;
   SIGNAL BU436_SCLR : STD_LOGIC;
   SIGNAL BU436_SSET : STD_LOGIC;
   SIGNAL BU436_SINIT : STD_LOGIC;
   SIGNAL BU436_O : STD_LOGIC;
   SIGNAL BU441_CLK : STD_LOGIC;
   SIGNAL BU441_SDIN : STD_LOGIC;
   SIGNAL BU441_Q : STD_LOGIC_VECTOR(12 DOWNTO 0);
   SIGNAL BU441_CE : STD_LOGIC;
   SIGNAL BU470_I : STD_LOGIC_VECTOR(3 DOWNTO 0);
   SIGNAL BU470_T : STD_LOGIC;
   SIGNAL BU470_EN : STD_LOGIC;
   SIGNAL BU470_Q : STD_LOGIC;
   SIGNAL BU470_CLK : STD_LOGIC;
   SIGNAL BU470_CE : STD_LOGIC;
   SIGNAL BU470_ACLR : STD_LOGIC;
   SIGNAL BU470_ASET : STD_LOGIC;
   SIGNAL BU470_AINIT : STD_LOGIC;
   SIGNAL BU470_SCLR : STD_LOGIC;
   SIGNAL BU470_SSET : STD_LOGIC;
   SIGNAL BU470_SINIT : STD_LOGIC;
   SIGNAL BU470_O : STD_LOGIC;
   SIGNAL BU475_CLK : STD_LOGIC;
   SIGNAL BU475_SDIN : STD_LOGIC;
   SIGNAL BU475_Q : STD_LOGIC_VECTOR(13 DOWNTO 0);
   SIGNAL BU475_CE : STD_LOGIC;
   SIGNAL BU637_A : STD_LOGIC_VECTOR(7 DOWNTO 0);
   SIGNAL BU637_B : STD_LOGIC_VECTOR(7 DOWNTO 0);
   SIGNAL BU637_Q : STD_LOGIC_VECTOR(8 DOWNTO 0);
   SIGNAL BU637_CLK : STD_LOGIC;
   SIGNAL BU637_CE : STD_LOGIC;
   SIGNAL BU560_I : STD_LOGIC_VECTOR(1 DOWNTO 0);
   SIGNAL BU560_T : STD_LOGIC;
   SIGNAL BU560_EN : STD_LOGIC;
   SIGNAL BU560_Q : STD_LOGIC;
   SIGNAL BU560_CLK : STD_LOGIC;
   SIGNAL BU560_CE : STD_LOGIC;
   SIGNAL BU560_ACLR : STD_LOGIC;
   SIGNAL BU560_ASET : STD_LOGIC;
   SIGNAL BU560_AINIT : STD_LOGIC;
   SIGNAL BU560_SCLR : STD_LOGIC;
   SIGNAL BU560_SSET : STD_LOGIC;
   SIGNAL BU560_SINIT : STD_LOGIC;
   SIGNAL BU560_O : STD_LOGIC;
   SIGNAL BU565_CLK : STD_LOGIC;
   SIGNAL BU565_SDIN : STD_LOGIC;
   SIGNAL BU565_Q : STD_LOGIC_VECTOR(14 DOWNTO 0);
   SIGNAL BU565_CE : STD_LOGIC;
   SIGNAL BU598_I : STD_LOGIC_VECTOR(3 DOWNTO 0);
   SIGNAL BU598_T : STD_LOGIC;
   SIGNAL BU598_EN : STD_LOGIC;
   SIGNAL BU598_Q : STD_LOGIC;
   SIGNAL BU598_CLK : STD_LOGIC;
   SIGNAL BU598_CE : STD_LOGIC;
   SIGNAL BU598_ACLR : STD_LOGIC;
   SIGNAL BU598_ASET : STD_LOGIC;
   SIGNAL BU598_AINIT : STD_LOGIC;
   SIGNAL BU598_SCLR : STD_LOGIC;
   SIGNAL BU598_SSET : STD_LOGIC;
   SIGNAL BU598_SINIT : STD_LOGIC;
   SIGNAL BU598_O : STD_LOGIC;
   SIGNAL BU603_CLK : STD_LOGIC;
   SIGNAL BU603_SDIN : STD_LOGIC;
   SIGNAL BU603_Q : STD_LOGIC_VECTOR(15 DOWNTO 0);
   SIGNAL BU603_CE : STD_LOGIC;
   SIGNAL BU884_D : STD_LOGIC_VECTOR(13 DOWNTO 0);
   SIGNAL BU884_Q : STD_LOGIC_VECTOR(13 DOWNTO 0);
   SIGNAL BU884_CLK : STD_LOGIC;
   SIGNAL BU884_CE : STD_LOGIC;
   SIGNAL BU915_A : STD_LOGIC_VECTOR(11 DOWNTO 0);
   SIGNAL BU915_BYPASS : STD_LOGIC;
   SIGNAL BU915_CLK : STD_LOGIC;
   SIGNAL BU915_Q : STD_LOGIC_VECTOR(12 DOWNTO 0);
   SIGNAL BU915_CE : STD_LOGIC;
   SIGNAL BU1008_CLK : STD_LOGIC;
   SIGNAL BU1008_D : STD_LOGIC_VECTOR(0 DOWNTO 0);
   SIGNAL BU1008_Q : STD_LOGIC_VECTOR(0 DOWNTO 0);
   SIGNAL BU1008_CE : STD_LOGIC;
   SIGNAL BU1016_CLK : STD_LOGIC;
   SIGNAL BU1016_D : STD_LOGIC_VECTOR(0 DOWNTO 0);
   SIGNAL BU1016_Q : STD_LOGIC_VECTOR(0 DOWNTO 0);
   SIGNAL BU1016_CE : STD_LOGIC;
   SIGNAL BU1027_I0 : STD_LOGIC;
   SIGNAL BU1027_I1 : STD_LOGIC;
   SIGNAL BU1027_I2 : STD_LOGIC;
   SIGNAL BU1027_I3 : STD_LOGIC;
   SIGNAL BU1027_O : STD_LOGIC;
   SIGNAL BU1028_D : STD_LOGIC;
   SIGNAL BU1028_C : STD_LOGIC;
   SIGNAL BU1028_CE : STD_LOGIC;
   SIGNAL BU1028_PRE : STD_LOGIC;
   SIGNAL BU1028_Q : STD_LOGIC;
   SIGNAL BU1032_I0 : STD_LOGIC;
   SIGNAL BU1032_I1 : STD_LOGIC;
   SIGNAL BU1032_I2 : STD_LOGIC;
   SIGNAL BU1032_I3 : STD_LOGIC;
   SIGNAL BU1032_O : STD_LOGIC;
   SIGNAL BU1033_D : STD_LOGIC;
   SIGNAL BU1033_C : STD_LOGIC;
   SIGNAL BU1033_CE : STD_LOGIC;
   SIGNAL BU1033_Q : STD_LOGIC;
   SIGNAL BU1037_I0 : STD_LOGIC;
   SIGNAL BU1037_I1 : STD_LOGIC;
   SIGNAL BU1037_I2 : STD_LOGIC;
   SIGNAL BU1037_I3 : STD_LOGIC;
   SIGNAL BU1037_O : STD_LOGIC;
   SIGNAL BU1038_D : STD_LOGIC;
   SIGNAL BU1038_C : STD_LOGIC;
   SIGNAL BU1038_CE : STD_LOGIC;
   SIGNAL BU1038_Q : STD_LOGIC;
   SIGNAL BU1040_A : STD_LOGIC_VECTOR(11 DOWNTO 0);
   SIGNAL BU1040_CLK : STD_LOGIC;
   SIGNAL BU1040_CE : STD_LOGIC;
   SIGNAL BU1040_ACLR : STD_LOGIC;
   SIGNAL BU1040_QA_GE_B : STD_LOGIC;
   SIGNAL BU1082_A : STD_LOGIC_VECTOR(11 DOWNTO 0);
   SIGNAL BU1082_CLK : STD_LOGIC;
   SIGNAL BU1082_CE : STD_LOGIC;
   SIGNAL BU1082_ACLR : STD_LOGIC;
   SIGNAL BU1082_QA_EQ_B : STD_LOGIC;
   SIGNAL BU1101_D : STD_LOGIC_VECTOR(13 DOWNTO 0);
   SIGNAL BU1101_Q : STD_LOGIC_VECTOR(13 DOWNTO 0);
   SIGNAL BU1101_CLK : STD_LOGIC;
   SIGNAL BU1101_CE : STD_LOGIC;
   SIGNAL BU1132_A : STD_LOGIC_VECTOR(11 DOWNTO 0);
   SIGNAL BU1132_BYPASS : STD_LOGIC;
   SIGNAL BU1132_CLK : STD_LOGIC;
   SIGNAL BU1132_Q : STD_LOGIC_VECTOR(12 DOWNTO 0);
   SIGNAL BU1132_CE : STD_LOGIC;
   SIGNAL BU1227_CLK : STD_LOGIC;
   SIGNAL BU1227_D : STD_LOGIC_VECTOR(0 DOWNTO 0);
   SIGNAL BU1227_Q : STD_LOGIC_VECTOR(0 DOWNTO 0);
   SIGNAL BU1227_CE : STD_LOGIC;
   SIGNAL BU1235_CLK : STD_LOGIC;
   SIGNAL BU1235_D : STD_LOGIC_VECTOR(0 DOWNTO 0);
   SIGNAL BU1235_Q : STD_LOGIC_VECTOR(0 DOWNTO 0);
   SIGNAL BU1235_CE : STD_LOGIC;
   SIGNAL BU1246_I0 : STD_LOGIC;
   SIGNAL BU1246_I1 : STD_LOGIC;
   SIGNAL BU1246_I2 : STD_LOGIC;
   SIGNAL BU1246_I3 : STD_LOGIC;
   SIGNAL BU1246_O : STD_LOGIC;
   SIGNAL BU1247_D : STD_LOGIC;
   SIGNAL BU1247_C : STD_LOGIC;
   SIGNAL BU1247_CE : STD_LOGIC;
   SIGNAL BU1247_PRE : STD_LOGIC;
   SIGNAL BU1247_Q : STD_LOGIC;
   SIGNAL BU1251_I0 : STD_LOGIC;
   SIGNAL BU1251_I1 : STD_LOGIC;
   SIGNAL BU1251_I2 : STD_LOGIC;
   SIGNAL BU1251_I3 : STD_LOGIC;
   SIGNAL BU1251_O : STD_LOGIC;
   SIGNAL BU1252_D : STD_LOGIC;
   SIGNAL BU1252_C : STD_LOGIC;
   SIGNAL BU1252_CE : STD_LOGIC;
   SIGNAL BU1252_Q : STD_LOGIC;
   SIGNAL BU1256_I0 : STD_LOGIC;
   SIGNAL BU1256_I1 : STD_LOGIC;
   SIGNAL BU1256_I2 : STD_LOGIC;
   SIGNAL BU1256_I3 : STD_LOGIC;
   SIGNAL BU1256_O : STD_LOGIC;
   SIGNAL BU1257_D : STD_LOGIC;
   SIGNAL BU1257_C : STD_LOGIC;
   SIGNAL BU1257_CE : STD_LOGIC;
   SIGNAL BU1257_Q : STD_LOGIC;
   SIGNAL BU1259_A : STD_LOGIC_VECTOR(11 DOWNTO 0);
   SIGNAL BU1259_CLK : STD_LOGIC;
   SIGNAL BU1259_CE : STD_LOGIC;
   SIGNAL BU1259_ACLR : STD_LOGIC;
   SIGNAL BU1259_QA_GE_B : STD_LOGIC;
   SIGNAL BU1301_A : STD_LOGIC_VECTOR(11 DOWNTO 0);
   SIGNAL BU1301_CLK : STD_LOGIC;
   SIGNAL BU1301_CE : STD_LOGIC;
   SIGNAL BU1301_ACLR : STD_LOGIC;
   SIGNAL BU1301_QA_EQ_B : STD_LOGIC;
   SIGNAL BU866_addra : STD_LOGIC_VECTOR(11 DOWNTO 0);
   SIGNAL BU866_addrb : STD_LOGIC_VECTOR(11 DOWNTO 0);
   SIGNAL BU866_clka : STD_LOGIC;
   SIGNAL BU866_clkb : STD_LOGIC;
   SIGNAL BU866_dina : STD_LOGIC_VECTOR(14 DOWNTO 0);
   SIGNAL BU866_dinb : STD_LOGIC_VECTOR(14 DOWNTO 0);
   SIGNAL BU866_douta : STD_LOGIC_VECTOR(14 DOWNTO 0);
   SIGNAL BU866_doutb : STD_LOGIC_VECTOR(14 DOWNTO 0);
   SIGNAL BU866_ena : STD_LOGIC;
   SIGNAL BU866_enb : STD_LOGIC;
   SIGNAL BU866_nda : STD_LOGIC;
   SIGNAL BU866_ndb : STD_LOGIC;
   SIGNAL BU866_rfda : STD_LOGIC;
   SIGNAL BU866_rfdb : STD_LOGIC;
   SIGNAL BU866_rdya : STD_LOGIC;
   SIGNAL BU866_rdyb : STD_LOGIC;
   SIGNAL BU866_sinita : STD_LOGIC;
   SIGNAL BU866_sinitb : STD_LOGIC;
   SIGNAL BU866_wea : STD_LOGIC;
   SIGNAL BU866_web : STD_LOGIC;
   SIGNAL BU1320_A : STD_LOGIC_VECTOR(15 DOWNTO 0);
   SIGNAL BU1320_B : STD_LOGIC_VECTOR(15 DOWNTO 0);
   SIGNAL BU1320_C_IN : STD_LOGIC;
   SIGNAL BU1320_ADD : STD_LOGIC;
   SIGNAL BU1320_Q : STD_LOGIC_VECTOR(15 DOWNTO 0);
   SIGNAL BU1320_CLK : STD_LOGIC;
   SIGNAL BU1320_CE : STD_LOGIC;
   SIGNAL BU1417_CLK : STD_LOGIC;
   SIGNAL BU1417_SDIN : STD_LOGIC;
   SIGNAL BU1417_SDOUT : STD_LOGIC;
   SIGNAL BU1417_CE : STD_LOGIC;
   SIGNAL BU1429_I0 : STD_LOGIC;
   SIGNAL BU1429_I1 : STD_LOGIC;
   SIGNAL BU1429_I2 : STD_LOGIC;
   SIGNAL BU1429_I3 : STD_LOGIC;
   SIGNAL BU1429_O : STD_LOGIC;
   SIGNAL BU1432_A : STD_LOGIC_VECTOR(15 DOWNTO 0);
   SIGNAL BU1432_B : STD_LOGIC_VECTOR(15 DOWNTO 0);
   SIGNAL BU1432_C_IN : STD_LOGIC;
   SIGNAL BU1432_ADD : STD_LOGIC;
   SIGNAL BU1432_Q : STD_LOGIC_VECTOR(15 DOWNTO 0);
   SIGNAL BU1432_CLK : STD_LOGIC;
   SIGNAL BU1432_CE : STD_LOGIC;
   SIGNAL n0 : STD_LOGIC := '0';
   SIGNAL n1 : STD_LOGIC := '1';
   SIGNAL n2 : STD_LOGIC;
   SIGNAL n19 : STD_LOGIC;
   SIGNAL n20 : STD_LOGIC;
   SIGNAL n21 : STD_LOGIC;
   SIGNAL n22 : STD_LOGIC;
   SIGNAL n23 : STD_LOGIC;
   SIGNAL n24 : STD_LOGIC;
   SIGNAL n25 : STD_LOGIC;
   SIGNAL n36 : STD_LOGIC;
   SIGNAL n37 : STD_LOGIC;
   SIGNAL n38 : STD_LOGIC;
   SIGNAL n39 : STD_LOGIC;
   SIGNAL n40 : STD_LOGIC;
   SIGNAL n41 : STD_LOGIC;
   SIGNAL n42 : STD_LOGIC;
   SIGNAL n43 : STD_LOGIC;
   SIGNAL n44 : STD_LOGIC;
   SIGNAL n45 : STD_LOGIC;
   SIGNAL n46 : STD_LOGIC;
   SIGNAL n47 : STD_LOGIC;
   SIGNAL n48 : STD_LOGIC;
   SIGNAL n49 : STD_LOGIC;
   SIGNAL n50 : STD_LOGIC;
   SIGNAL n51 : STD_LOGIC;
   SIGNAL n52 : STD_LOGIC;
   SIGNAL n53 : STD_LOGIC;
   SIGNAL n54 : STD_LOGIC;
   SIGNAL n55 : STD_LOGIC;
   SIGNAL n56 : STD_LOGIC;
   SIGNAL n57 : STD_LOGIC;
   SIGNAL n58 : STD_LOGIC;
   SIGNAL n59 : STD_LOGIC;
   SIGNAL n60 : STD_LOGIC;
   SIGNAL n63 : STD_LOGIC;
   SIGNAL n64 : STD_LOGIC;
   SIGNAL n65 : STD_LOGIC;
   SIGNAL n66 : STD_LOGIC;
   SIGNAL n67 : STD_LOGIC;
   SIGNAL n68 : STD_LOGIC;
   SIGNAL n69 : STD_LOGIC;
   SIGNAL n70 : STD_LOGIC;
   SIGNAL n71 : STD_LOGIC;
   SIGNAL n72 : STD_LOGIC;
   SIGNAL n73 : STD_LOGIC;
   SIGNAL n74 : STD_LOGIC;
   SIGNAL n75 : STD_LOGIC;
   SIGNAL n76 : STD_LOGIC;
   SIGNAL n77 : STD_LOGIC;
   SIGNAL n78 : STD_LOGIC;
   SIGNAL n79 : STD_LOGIC;
   SIGNAL n80 : STD_LOGIC;
   SIGNAL n81 : STD_LOGIC;
   SIGNAL n82 : STD_LOGIC;
   SIGNAL n83 : STD_LOGIC;
   SIGNAL n84 : STD_LOGIC;
   SIGNAL n85 : STD_LOGIC;
   SIGNAL n86 : STD_LOGIC;
   SIGNAL n87 : STD_LOGIC;
   SIGNAL n88 : STD_LOGIC;
   SIGNAL n89 : STD_LOGIC;
   SIGNAL n90 : STD_LOGIC;
   SIGNAL n91 : STD_LOGIC;
   SIGNAL n92 : STD_LOGIC;
   SIGNAL n93 : STD_LOGIC;
   SIGNAL n94 : STD_LOGIC;
   SIGNAL n95 : STD_LOGIC;
   SIGNAL n96 : STD_LOGIC;
   SIGNAL n97 : STD_LOGIC;
   SIGNAL n98 : STD_LOGIC;
   SIGNAL n99 : STD_LOGIC;
   SIGNAL n100 : STD_LOGIC;
   SIGNAL n101 : STD_LOGIC;
   SIGNAL n102 : STD_LOGIC;
   SIGNAL n103 : STD_LOGIC;
   SIGNAL n104 : STD_LOGIC;
   SIGNAL n105 : STD_LOGIC;
   SIGNAL n106 : STD_LOGIC;
   SIGNAL n107 : STD_LOGIC;
   SIGNAL n108 : STD_LOGIC;
   SIGNAL n109 : STD_LOGIC;
   SIGNAL n110 : STD_LOGIC;
   SIGNAL n144 : STD_LOGIC;
   SIGNAL n145 : STD_LOGIC;
   SIGNAL n146 : STD_LOGIC;
   SIGNAL n147 : STD_LOGIC;
   SIGNAL n148 : STD_LOGIC;
   SIGNAL n149 : STD_LOGIC;
   SIGNAL n150 : STD_LOGIC;
   SIGNAL n151 : STD_LOGIC;
   SIGNAL n152 : STD_LOGIC;
   SIGNAL n153 : STD_LOGIC;
   SIGNAL n154 : STD_LOGIC;
   SIGNAL n155 : STD_LOGIC;
   SIGNAL n156 : STD_LOGIC;
   SIGNAL n157 : STD_LOGIC;
   SIGNAL n158 : STD_LOGIC;
   SIGNAL n159 : STD_LOGIC;
   SIGNAL n160 : STD_LOGIC;
   SIGNAL n161 : STD_LOGIC;
   SIGNAL n162 : STD_LOGIC;
   SIGNAL n163 : STD_LOGIC;
   SIGNAL n164 : STD_LOGIC;
   SIGNAL n165 : STD_LOGIC;
   SIGNAL n166 : STD_LOGIC;
   SIGNAL n167 : STD_LOGIC;
   SIGNAL n168 : STD_LOGIC;
   SIGNAL n175 : STD_LOGIC;
   SIGNAL n176 : STD_LOGIC;
   SIGNAL n177 : STD_LOGIC;
   SIGNAL n178 : STD_LOGIC;
   SIGNAL n179 : STD_LOGIC;
   SIGNAL n180 : STD_LOGIC;
   SIGNAL n181 : STD_LOGIC;
   SIGNAL n182 : STD_LOGIC;
   SIGNAL n183 : STD_LOGIC;
   SIGNAL n184 : STD_LOGIC;
   SIGNAL n185 : STD_LOGIC;
   SIGNAL n186 : STD_LOGIC;