ddsqam.veo

基于FPGA的16QAM调制与解调的设计与实现源代码

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// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.

//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
ddsqam YourInstanceName (
	.DATA(DATA), // Bus [24 : 0] 
	.WE(WE),
	.A(A), // Bus [4 : 0] 
	.CLK(CLK),
	.CE(CE),
	.SINE(SINE), // Bus [15 : 0] 
	.COSINE(COSINE)); // Bus [15 : 0] 

// INST_TAG_END ------ End INSTANTIATION Template ---------

// You must compile the wrapper file ddsqam.v when simulating
// the core, ddsqam. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".