ddsqam.v

基于FPGA的16QAM调制与解调的设计与实现源代码

         .AINIT(BU598_AINIT),
         .SCLR(BU598_SCLR),
         .SSET(BU598_SSET),
         .SINIT(BU598_SINIT),
         .O(BU598_O)
      );

      wire BU603_CLK;
         assign BU603_CLK = n175;
      wire BU603_SDIN;
         assign BU603_SDIN = n1858;
      wire [15 : 0] BU603_Q;
         assign n1859 = BU603_Q[0];
         assign n1860 = BU603_Q[2];
         assign n1850 = BU603_Q[8];
         assign n1851 = BU603_Q[9];
         assign n1852 = BU603_Q[10];
         assign n1853 = BU603_Q[11];
         assign n1854 = BU603_Q[12];
         assign n1855 = BU603_Q[13];
         assign n1856 = BU603_Q[14];
         assign n1857 = BU603_Q[15];
      wire BU603_CE;
         assign BU603_CE = n176;
      C_SHIFT_FD_V7_0 #(
         "1000000000000000"    /* c_ainit_val*/,
         0    /* c_enable_rlocs*/,
         5    /* c_fill_data*/,
         0    /* c_has_aclr*/,
         0    /* c_has_ainit*/,
         0    /* c_has_aset*/,
         1    /* c_has_ce*/,
         0    /* c_has_d*/,
         0    /* c_has_lsb_2_msb*/,
         1    /* c_has_q*/,
         0    /* c_has_sclr*/,
         1    /* c_has_sdin*/,
         0    /* c_has_sdout*/,
         0    /* c_has_sinit*/,
         0    /* c_has_sset*/,
         0    /* c_shift_type*/,
         "1000000000000000"    /* c_sinit_val*/,
         0    /* c_sync_enable*/,
         0    /* c_sync_priority*/,
         16    /* c_width*/
      )
      BU603(
         .CLK(BU603_CLK),
         .SDIN(BU603_SDIN),
         .Q(BU603_Q),
         .CE(BU603_CE)
      );

      wire [13 : 0] BU884_D;
         assign BU884_D[0] = n87;
         assign BU884_D[1] = n88;
         assign BU884_D[2] = n89;
         assign BU884_D[3] = n90;
         assign BU884_D[4] = n91;
         assign BU884_D[5] = n92;
         assign BU884_D[6] = n93;
         assign BU884_D[7] = n94;
         assign BU884_D[8] = n95;
         assign BU884_D[9] = n96;
         assign BU884_D[10] = n97;
         assign BU884_D[11] = n98;
         assign BU884_D[12] = n99;
         assign BU884_D[13] = n100;
      wire [13 : 0] BU884_Q;
         assign n2547 = BU884_Q[0];
         assign n2548 = BU884_Q[1];
         assign n2549 = BU884_Q[2];
         assign n2550 = BU884_Q[3];
         assign n2551 = BU884_Q[4];
         assign n2552 = BU884_Q[5];
         assign n2553 = BU884_Q[6];
         assign n2554 = BU884_Q[7];
         assign n2555 = BU884_Q[8];
         assign n2556 = BU884_Q[9];
         assign n2557 = BU884_Q[10];
         assign n2558 = BU884_Q[11];
         assign n2559 = BU884_Q[12];
         assign n2560 = BU884_Q[13];
      wire BU884_CLK;
         assign BU884_CLK = n175;
      wire BU884_CE;
         assign BU884_CE = n176;
      C_REG_FD_V7_0 #(
         "00000000000000"    /* c_ainit_val*/,
         0    /* c_enable_rlocs*/,
         0    /* c_has_aclr*/,
         0    /* c_has_ainit*/,
         0    /* c_has_aset*/,
         1    /* c_has_ce*/,
         0    /* c_has_sclr*/,
         0    /* c_has_sinit*/,
         0    /* c_has_sset*/,
         "00000000000000"    /* c_sinit_val*/,
         0    /* c_sync_enable*/,
         0    /* c_sync_priority*/,
         14    /* c_width*/
      )
      BU884(
         .D(BU884_D),
         .Q(BU884_Q),
         .CLK(BU884_CLK),
         .CE(BU884_CE)
      );

      wire [11 : 0] BU915_A;
         assign BU915_A[0] = n2547;
         assign BU915_A[1] = n2548;
         assign BU915_A[2] = n2549;
         assign BU915_A[3] = n2550;
         assign BU915_A[4] = n2551;
         assign BU915_A[5] = n2552;
         assign BU915_A[6] = n2553;
         assign BU915_A[7] = n2554;
         assign BU915_A[8] = n2555;
         assign BU915_A[9] = n2556;
         assign BU915_A[10] = n2557;
         assign BU915_A[11] = n2558;
      wire BU915_BYPASS;
         assign BU915_BYPASS = n2559;
      wire BU915_CLK;
         assign BU915_CLK = n175;
      wire [12 : 0] BU915_Q;
         assign n2587 = BU915_Q[0];
         assign n2588 = BU915_Q[1];
         assign n2589 = BU915_Q[2];
         assign n2590 = BU915_Q[3];
         assign n2591 = BU915_Q[4];
         assign n2592 = BU915_Q[5];
         assign n2593 = BU915_Q[6];
         assign n2594 = BU915_Q[7];
         assign n2595 = BU915_Q[8];
         assign n2596 = BU915_Q[9];
         assign n2597 = BU915_Q[10];
         assign n2598 = BU915_Q[11];
      wire BU915_CE;
         assign BU915_CE = n176;
      C_TWOS_COMP_V7_0 #(
         "0000000000000"    /* c_ainit_val*/,
         1    /* c_bypass_enable*/,
         1    /* c_bypass_low*/,
         0    /* c_enable_rlocs*/,
         0    /* c_has_aclr*/,
         0    /* c_has_ainit*/,
         0    /* c_has_aset*/,
         1    /* c_has_bypass*/,
         1    /* c_has_ce*/,
         1    /* c_has_q*/,
         0    /* c_has_s*/,
         0    /* c_has_sclr*/,
         0    /* c_has_sinit*/,
         0    /* c_has_sset*/,
         0    /* c_pipe_stages*/,
         "0000000000000"    /* c_sinit_val*/,
         0    /* c_sync_enable*/,
         0    /* c_sync_priority*/,
         12    /* c_width*/
      )
      BU915(
         .A(BU915_A),
         .BYPASS(BU915_BYPASS),
         .CLK(BU915_CLK),
         .Q(BU915_Q),
         .CE(BU915_CE)
      );

      wire BU1008_CLK;
         assign BU1008_CLK = n175;
      wire [0 : 0] BU1008_D;
         assign BU1008_D[0] = n2560;
      wire [0 : 0] BU1008_Q;
         assign n2561 = BU1008_Q[0];
      wire BU1008_CE;
         assign BU1008_CE = n176;
      C_SHIFT_RAM_V7_0 #(
         1    /* c_addr_width*/,
         "0"    /* c_ainit_val*/,
         "0"    /* c_default_data*/,
         2    /* c_default_data_radix*/,
         2    /* c_depth*/,
         0    /* c_enable_rlocs*/,
         0    /* c_generate_mif*/,
         0    /* c_has_a*/,
         0    /* c_has_aclr*/,
         0    /* c_has_ainit*/,
         0    /* c_has_aset*/,
         1    /* c_has_ce*/,
         0    /* c_has_sclr*/,
         0    /* c_has_sinit*/,
         0    /* c_has_sset*/,
         "null"    /* c_mem_init_file*/,
         2    /* c_mem_init_radix*/,
         0    /* c_read_mif*/,
         1    /* c_reg_last_bit*/,
         0    /* c_shift_type*/,
         "0"    /* c_sinit_val*/,
         0    /* c_sync_enable*/,
         0    /* c_sync_priority*/,
         1    /* c_width*/
      )
      BU1008(
         .CLK(BU1008_CLK),
         .D(BU1008_D),
         .Q(BU1008_Q),
         .CE(BU1008_CE)
      );

      wire BU1016_CLK;
         assign BU1016_CLK = n175;
      wire [0 : 0] BU1016_D;
         assign BU1016_D[0] = n2559;
      wire [0 : 0] BU1016_Q;
         assign n2562 = BU1016_Q[0];
      wire BU1016_CE;
         assign BU1016_CE = n176;
      C_SHIFT_RAM_V7_0 #(
         1    /* c_addr_width*/,
         "0"    /* c_ainit_val*/,
         "0"    /* c_default_data*/,
         2    /* c_default_data_radix*/,
         2    /* c_depth*/,
         0    /* c_enable_rlocs*/,
         0    /* c_generate_mif*/,
         0    /* c_has_a*/,
         0    /* c_has_aclr*/,
         0    /* c_has_ainit*/,
         0    /* c_has_aset*/,
         1    /* c_has_ce*/,
         0    /* c_has_sclr*/,
         0    /* c_has_sinit*/,
         0    /* c_has_sset*/,
         "null"    /* c_mem_init_file*/,
         2    /* c_mem_init_radix*/,
         0    /* c_read_mif*/,
         1    /* c_reg_last_bit*/,
         0    /* c_shift_type*/,
         "0"    /* c_sinit_val*/,
         0    /* c_sync_enable*/,
         0    /* c_sync_priority*/,
         1    /* c_width*/
      )
      BU1016(
         .CLK(BU1016_CLK),
         .D(BU1016_D),
         .Q(BU1016_Q),
         .CE(BU1016_CE)
      );

      defparam BU1027.INIT = 'h9595;
      wire BU1027_I0;
         assign BU1027_I0 = n2561;
      wire BU1027_I1;
         assign BU1027_I1 = n2562;
      wire BU1027_I2;
         assign BU1027_I2 = n2603;
      wire BU1027_I3;
         assign BU1027_I3 = 1'b0;
      wire BU1027_O;
         assign n3020 = BU1027_O;
      LUT4       BU1027(
         .I0(BU1027_I0),
         .I1(BU1027_I1),
         .I2(BU1027_I2),
         .I3(BU1027_I3),
         .O(BU1027_O)
      );

      wire BU1028_D;
         assign BU1028_D = n3020;
      wire BU1028_C;
         assign BU1028_C = n175;
      wire BU1028_CE;
         assign BU1028_CE = n176;
      wire BU1028_PRE;
         assign BU1028_PRE = 1'b0;
      wire BU1028_Q;
         assign n2605 = BU1028_Q;
      FDPE       BU1028(
         .D(BU1028_D),
         .C(BU1028_C),
         .CE(BU1028_CE),
         .PRE(BU1028_PRE),
         .Q(BU1028_Q)
      );

      defparam BU1032.INIT = 'h002a;
      wire BU1032_I0;
         assign BU1032_I0 = n2561;
      wire BU1032_I1;
         assign BU1032_I1 = n2562;
      wire BU1032_I2;
         assign BU1032_I2 = n2603;
      wire BU1032_I3;
         assign BU1032_I3 = n2604;
      wire BU1032_O;
         assign n3039 = BU1032_O;
      LUT4       BU1032(
         .I0(BU1032_I0),
         .I1(BU1032_I1),
         .I2(BU1032_I2),
         .I3(BU1032_I3),
         .O(BU1032_O)
      );

      wire BU1033_D;
         assign BU1033_D = n3039;
      wire BU1033_C;
         assign BU1033_C = n175;
      wire BU1033_CE;
         assign BU1033_CE = n176;
      wire BU1033_Q;
         assign n2606 = BU1033_Q;
      FDE       BU1033(
         .D(BU1033_D),
         .C(BU1033_C),
         .CE(BU1033_CE),
         .Q(BU1033_Q)
      );

      defparam BU1037.INIT = 'hc0c0;
      wire BU1037_I0;
         assign BU1037_I0 = 1'b0;
      wire BU1037_I1;
         assign BU1037_I1 = n2562;
      wire BU1037_I2;
         assign BU1037_I2 = n2603;
      wire BU1037_I3;
         assign BU1037_I3 = 1'b0;
      wire BU1037_O;
         assign n3057 = BU1037_O;
      LUT4       BU1037(
         .I0(BU1037_I0),
         .I1(BU1037_I1),
         .I2(BU1037_I2),
         .I3(BU1037_I3),
         .O(BU1037_O)
      );

      wire BU1038_D;
         assign BU1038_D = n3057;
      wire BU1038_C;
         assign BU1038_C = n175;
      wire BU1038_CE;
         assign BU1038_CE = n176;
      wire BU1038_Q;
         assign n2602 = BU1038_Q;
      FDE       BU1038(
         .D(BU1038_D),
         .C(BU1038_C),
         .CE(BU1038_CE),
         .Q(BU1038_Q)
      );

      wire [11 : 0] BU1040_A;
         assign BU1040_A[0] = n2587;
         assign BU1040_A[1] = n2588;
         assign BU1040_A[2] = n2589;
         assign BU1040_A[3] = n2590;
         assign BU1040_A[4] = n2591;
         assign BU1040_A[5] = n2592;
         assign BU1040_A[6] = n2593;
         assign BU1040_A[7] = n2594;
         assign BU1040_A[8] = n2595;
         assign BU1040_A[9] = n2596;
         assign BU1040_A[10] = n2597;
         assign BU1040_A[11] = n2598;
      wire BU1040_CLK;
         assign BU1040_CLK = n175;
      wire BU1040_CE;
         assign BU1040_CE = n176;
      wire BU1040_ACLR;
         assign BU1040_ACLR = 1'b0;
      wire BU1040_QA_GE_B;
         assign n2604 = BU1040_QA_GE_B;
      C_COMPARE_V7_0 #(
         "0"    /* c_ainit_val*/,
         1    /* c_b_constant*/,
         "111111110010"    /* c_b_value*/,
         1    /* c_data_type*/,
         0    /* c_enable_rlocs*/,
         1    /* c_has_aclr*/,
         0    /* c_has_aset*/,
         0    /* c_has_a_eq_b*/,
         0    /* c_has_a_ge_b*/,
         0    /* c_has_a_gt_b*/,
         0    /* c_has_a_le_b*/,
         0    /* c_has_a_lt_b*/,
         0    /* c_has_a_ne_b*/,
         1    /* c_has_ce*/,
         0    /* c_has_qa_eq_b*/,
         1    /* c_has_qa_ge_b*/,
         0    /* c_has_qa_gt_b*/,
         0    /* c_has_qa_le_b*/,
         0    /* c_has_qa_lt_b*/,
         0    /* c_has_qa_ne_b*/,
         0    /* c_has_sclr*/,
         0    /* c_has_sset*/,
         0    /* c_pipe_stages*/,
         0    /* c_sync_enable*/,
         0    /* c_sync_priority*/,
         12    /* c_width*/
      )
      BU1040(
         .A(BU1040_A),
         .CLK(BU1040_CLK),
         .CE(BU1040_CE),
         .ACLR(BU1040_ACLR),
         .QA_GE_B(BU1040_QA_GE_B)
      );

      wire [11 : 0] BU1082_A;
         assign BU1082_A[0] = n2587;
         assign BU1082_A[1] = n2588;
         assign BU1082_A[2] = n2589;
         assign BU1082_A[3] = n2590;
         assign BU1082_A[4] = n2591;
         assign BU1082_A[5] = n2592;
         assign BU1082_A[6] = n2593;
         assign BU1082_A[7] = n2594;
         assign BU1082_A[8] = n2595;
         assign BU1082_A[9] = n2596;
         assign BU1082_A[10] = n2597;
         assign BU1082_A[11] = n2598;
      wire BU1082_CLK;
         assign BU1082_CLK = n175;
      wire BU1082_CE;
         assign BU1082_CE = n176;
      wire BU1082_ACLR;
         assign BU1082_ACLR = 1'b0;
      wire BU1082_QA_EQ_B;
         assign n2603 = BU1082_QA_EQ_B;
      C_COMPARE_V7_0 #(
         "0"    /* c_ainit_val*/,
         1    /* c_b_constant*/,
         "000000000000"    /* c_b_value*/,
         1    /* c_data_type*/,
         0    /* c_enable_rlocs*/,
         1    /* c_has_aclr*/,
         0    /* c_has_aset*/,
         0    /* c_has_a_eq_b*/,
         0    /* c_has_a_ge_b*/,
         0    /* c_has_a_gt_b*/,
         0    /* c_has_a_le_b*/,
         0    /* c_has_a_lt_b*/,
         0    /* c_has_a_ne_b*/,
         1    /* c_has_ce*/,
         1    /* c_has_qa_eq_b*/,
         0    /* c_has_qa_ge_b*/,
         0    /* c_has_qa_gt