ddsqam.v

基于FPGA的16QAM调制与解调的设计与实现源代码

         assign BU436_ACLR = 1'b0;
      wire BU436_ASET;
         assign BU436_ASET = 1'b0;
      wire BU436_AINIT;
         assign BU436_AINIT = 1'b0;
      wire BU436_SCLR;
         assign BU436_SCLR = 1'b0;
      wire BU436_SSET;
         assign BU436_SSET = 1'b0;
      wire BU436_SINIT;
         assign BU436_SINIT = 1'b0;
      wire BU436_O;
         assign n1702 = BU436_O;
      C_GATE_BIT_V7_0 #(
         "0"    /* c_ainit_val*/,
         0    /* c_enable_rlocs*/,
         4    /* c_gate_type*/,
         0    /* c_has_aclr*/,
         0    /* c_has_ainit*/,
         0    /* c_has_aset*/,
         0    /* c_has_ce*/,
         1    /* c_has_o*/,
         1    /* c_has_q*/,
         0    /* c_has_sclr*/,
         0    /* c_has_sinit*/,
         0    /* c_has_sset*/,
         4    /* c_inputs*/,
         "0000"    /* c_input_inv_mask*/,
         0    /* c_pipe_stages*/,
         "0"    /* c_sinit_val*/,
         0    /* c_sync_enable*/,
         1    /* c_sync_priority*/
      )
      BU436(
         .I(BU436_I),
         .T(BU436_T),
         .EN(BU436_EN),
         .Q(BU436_Q),
         .CLK(BU436_CLK),
         .CE(BU436_CE),
         .ACLR(BU436_ACLR),
         .ASET(BU436_ASET),
         .AINIT(BU436_AINIT),
         .SCLR(BU436_SCLR),
         .SSET(BU436_SSET),
         .SINIT(BU436_SINIT),
         .O(BU436_O)
      );

      wire BU441_CLK;
         assign BU441_CLK = n175;
      wire BU441_SDIN;
         assign BU441_SDIN = n1702;
      wire [12 : 0] BU441_Q;
         assign n1703 = BU441_Q[0];
         assign n1704 = BU441_Q[2];
         assign n1705 = BU441_Q[3];
         assign n1694 = BU441_Q[5];
         assign n1695 = BU441_Q[6];
         assign n1696 = BU441_Q[7];
         assign n1697 = BU441_Q[8];
         assign n1698 = BU441_Q[9];
         assign n1699 = BU441_Q[10];
         assign n1700 = BU441_Q[11];
         assign n1701 = BU441_Q[12];
      wire BU441_CE;
         assign BU441_CE = n176;
      C_SHIFT_FD_V7_0 #(
         "1000000000000"    /* c_ainit_val*/,
         0    /* c_enable_rlocs*/,
         5    /* c_fill_data*/,
         0    /* c_has_aclr*/,
         0    /* c_has_ainit*/,
         0    /* c_has_aset*/,
         1    /* c_has_ce*/,
         0    /* c_has_d*/,
         0    /* c_has_lsb_2_msb*/,
         1    /* c_has_q*/,
         0    /* c_has_sclr*/,
         1    /* c_has_sdin*/,
         0    /* c_has_sdout*/,
         0    /* c_has_sinit*/,
         0    /* c_has_sset*/,
         0    /* c_shift_type*/,
         "1000000000000"    /* c_sinit_val*/,
         0    /* c_sync_enable*/,
         0    /* c_sync_priority*/,
         13    /* c_width*/
      )
      BU441(
         .CLK(BU441_CLK),
         .SDIN(BU441_SDIN),
         .Q(BU441_Q),
         .CE(BU441_CE)
      );

      wire [3 : 0] BU470_I;
         assign BU470_I[0] = n1753;
         assign BU470_I[1] = n1754;
         assign BU470_I[2] = n1747;
         assign BU470_I[3] = n1751;
      wire BU470_T;
         assign BU470_T = 1'b0;
      wire BU470_EN;
         assign BU470_EN = 1'b0;
      wire BU470_Q;
      wire BU470_CLK;
         assign BU470_CLK = 1'b0;
      wire BU470_CE;
         assign BU470_CE = 1'b0;
      wire BU470_ACLR;
         assign BU470_ACLR = 1'b0;
      wire BU470_ASET;
         assign BU470_ASET = 1'b0;
      wire BU470_AINIT;
         assign BU470_AINIT = 1'b0;
      wire BU470_SCLR;
         assign BU470_SCLR = 1'b0;
      wire BU470_SSET;
         assign BU470_SSET = 1'b0;
      wire BU470_SINIT;
         assign BU470_SINIT = 1'b0;
      wire BU470_O;
         assign n1752 = BU470_O;
      C_GATE_BIT_V7_0 #(
         "0"    /* c_ainit_val*/,
         0    /* c_enable_rlocs*/,
         4    /* c_gate_type*/,
         0    /* c_has_aclr*/,
         0    /* c_has_ainit*/,
         0    /* c_has_aset*/,
         0    /* c_has_ce*/,
         1    /* c_has_o*/,
         1    /* c_has_q*/,
         0    /* c_has_sclr*/,
         0    /* c_has_sinit*/,
         0    /* c_has_sset*/,
         4    /* c_inputs*/,
         "0000"    /* c_input_inv_mask*/,
         0    /* c_pipe_stages*/,
         "0"    /* c_sinit_val*/,
         0    /* c_sync_enable*/,
         1    /* c_sync_priority*/
      )
      BU470(
         .I(BU470_I),
         .T(BU470_T),
         .EN(BU470_EN),
         .Q(BU470_Q),
         .CLK(BU470_CLK),
         .CE(BU470_CE),
         .ACLR(BU470_ACLR),
         .ASET(BU470_ASET),
         .AINIT(BU470_AINIT),
         .SCLR(BU470_SCLR),
         .SSET(BU470_SSET),
         .SINIT(BU470_SINIT),
         .O(BU470_O)
      );

      wire BU475_CLK;
         assign BU475_CLK = n175;
      wire BU475_SDIN;
         assign BU475_SDIN = n1752;
      wire [13 : 0] BU475_Q;
         assign n1753 = BU475_Q[0];
         assign n1754 = BU475_Q[5];
         assign n1744 = BU475_Q[6];
         assign n1745 = BU475_Q[7];
         assign n1746 = BU475_Q[8];
         assign n1747 = BU475_Q[9];
         assign n1748 = BU475_Q[10];
         assign n1749 = BU475_Q[11];
         assign n1750 = BU475_Q[12];
         assign n1751 = BU475_Q[13];
      wire BU475_CE;
         assign BU475_CE = n176;
      C_SHIFT_FD_V7_0 #(
         "10000000000000"    /* c_ainit_val*/,
         0    /* c_enable_rlocs*/,
         5    /* c_fill_data*/,
         0    /* c_has_aclr*/,
         0    /* c_has_ainit*/,
         0    /* c_has_aset*/,
         1    /* c_has_ce*/,
         0    /* c_has_d*/,
         0    /* c_has_lsb_2_msb*/,
         1    /* c_has_q*/,
         0    /* c_has_sclr*/,
         1    /* c_has_sdin*/,
         0    /* c_has_sdout*/,
         0    /* c_has_sinit*/,
         0    /* c_has_sset*/,
         0    /* c_shift_type*/,
         "10000000000000"    /* c_sinit_val*/,
         0    /* c_sync_enable*/,
         0    /* c_sync_priority*/,
         14    /* c_width*/
      )
      BU475(
         .CLK(BU475_CLK),
         .SDIN(BU475_SDIN),
         .Q(BU475_Q),
         .CE(BU475_CE)
      );

      wire [7 : 0] BU637_A;
         assign BU637_A[0] = n1804;
         assign BU637_A[1] = n1805;
         assign BU637_A[2] = n1806;
         assign BU637_A[3] = n1807;
         assign BU637_A[4] = n1808;
         assign BU637_A[5] = n1809;
         assign BU637_A[6] = n1810;
         assign BU637_A[7] = n1811;
      wire [7 : 0] BU637_B;
         assign BU637_B[0] = n1850;
         assign BU637_B[1] = n1851;
         assign BU637_B[2] = n1852;
         assign BU637_B[3] = n1853;
         assign BU637_B[4] = n1854;
         assign BU637_B[5] = n1855;
         assign BU637_B[6] = n1856;
         assign BU637_B[7] = n1857;
      wire [8 : 0] BU637_Q;
         assign n1903 = BU637_Q[0];
         assign n1904 = BU637_Q[1];
         assign n1905 = BU637_Q[2];
         assign n1906 = BU637_Q[3];
         assign n1907 = BU637_Q[4];
         assign n1908 = BU637_Q[5];
         assign n1909 = BU637_Q[6];
         assign n1910 = BU637_Q[7];
         assign n1911 = BU637_Q[8];
      wire BU637_CLK;
         assign BU637_CLK = n175;
      wire BU637_CE;
         assign BU637_CE = n176;
      C_ADDSUB_V7_0 #(
         0    /* c_add_mode*/,
         "000000000"    /* c_ainit_val*/,
         0    /* c_a_type*/,
         8    /* c_a_width*/,
         0    /* c_bypass_enable*/,
         0    /* c_bypass_low*/,
         0    /* c_b_constant*/,
         0    /* c_b_type*/,
         "000000000"    /* c_b_value*/,
         8    /* c_b_width*/,
         0    /* c_enable_rlocs*/,
         0    /* c_has_aclr*/,
         0    /* c_has_add*/,
         0    /* c_has_ainit*/,
         0    /* c_has_aset*/,
         0    /* c_has_a_signed*/,
         0    /* c_has_bypass*/,
         0    /* c_has_bypass_with_cin*/,
         0    /* c_has_b_in*/,
         0    /* c_has_b_out*/,
         0    /* c_has_b_signed*/,
         1    /* c_has_ce*/,
         0    /* c_has_c_in*/,
         0    /* c_has_c_out*/,
         0    /* c_has_ovfl*/,
         1    /* c_has_q*/,
         0    /* c_has_q_b_out*/,
         0    /* c_has_q_c_out*/,
         0    /* c_has_q_ovfl*/,
         1    /* c_has_s*/,
         0    /* c_has_sclr*/,
         0    /* c_has_sinit*/,
         0    /* c_has_sset*/,
         8    /* c_high_bit*/,
         1    /* c_latency*/,
         0    /* c_low_bit*/,
         9    /* c_out_width*/,
         0    /* c_pipe_stages*/,
         "000000000"    /* c_sinit_val*/,
         0    /* c_sync_enable*/,
         0    /* c_sync_priority*/
      )
      BU637(
         .A(BU637_A),
         .B(BU637_B),
         .Q(BU637_Q),
         .CLK(BU637_CLK),
         .CE(BU637_CE)
      );

      wire [1 : 0] BU560_I;
         assign BU560_I[0] = n1813;
         assign BU560_I[1] = n1811;
      wire BU560_T;
         assign BU560_T = 1'b0;
      wire BU560_EN;
         assign BU560_EN = 1'b0;
      wire BU560_Q;
      wire BU560_CLK;
         assign BU560_CLK = 1'b0;
      wire BU560_CE;
         assign BU560_CE = 1'b0;
      wire BU560_ACLR;
         assign BU560_ACLR = 1'b0;
      wire BU560_ASET;
         assign BU560_ASET = 1'b0;
      wire BU560_AINIT;
         assign BU560_AINIT = 1'b0;
      wire BU560_SCLR;
         assign BU560_SCLR = 1'b0;
      wire BU560_SSET;
         assign BU560_SSET = 1'b0;
      wire BU560_SINIT;
         assign BU560_SINIT = 1'b0;
      wire BU560_O;
         assign n1812 = BU560_O;
      C_GATE_BIT_V7_0 #(
         "0"    /* c_ainit_val*/,
         0    /* c_enable_rlocs*/,
         4    /* c_gate_type*/,
         0    /* c_has_aclr*/,
         0    /* c_has_ainit*/,
         0    /* c_has_aset*/,
         0    /* c_has_ce*/,
         1    /* c_has_o*/,
         1    /* c_has_q*/,
         0    /* c_has_sclr*/,
         0    /* c_has_sinit*/,
         0    /* c_has_sset*/,
         2    /* c_inputs*/,
         "00"    /* c_input_inv_mask*/,
         0    /* c_pipe_stages*/,
         "0"    /* c_sinit_val*/,
         0    /* c_sync_enable*/,
         1    /* c_sync_priority*/
      )
      BU560(
         .I(BU560_I),
         .T(BU560_T),
         .EN(BU560_EN),
         .Q(BU560_Q),
         .CLK(BU560_CLK),
         .CE(BU560_CE),
         .ACLR(BU560_ACLR),
         .ASET(BU560_ASET),
         .AINIT(BU560_AINIT),
         .SCLR(BU560_SCLR),
         .SSET(BU560_SSET),
         .SINIT(BU560_SINIT),
         .O(BU560_O)
      );

      wire BU565_CLK;
         assign BU565_CLK = n175;
      wire BU565_SDIN;
         assign BU565_SDIN = n1812;
      wire [14 : 0] BU565_Q;
         assign n1813 = BU565_Q[0];
         assign n1804 = BU565_Q[7];
         assign n1805 = BU565_Q[8];
         assign n1806 = BU565_Q[9];
         assign n1807 = BU565_Q[10];
         assign n1808 = BU565_Q[11];
         assign n1809 = BU565_Q[12];
         assign n1810 = BU565_Q[13];
         assign n1811 = BU565_Q[14];
      wire BU565_CE;
         assign BU565_CE = n176;
      C_SHIFT_FD_V7_0 #(
         "100000000000000"    /* c_ainit_val*/,
         0    /* c_enable_rlocs*/,
         5    /* c_fill_data*/,
         0    /* c_has_aclr*/,
         0    /* c_has_ainit*/,
         0    /* c_has_aset*/,
         1    /* c_has_ce*/,
         0    /* c_has_d*/,
         0    /* c_has_lsb_2_msb*/,
         1    /* c_has_q*/,
         0    /* c_has_sclr*/,
         1    /* c_has_sdin*/,
         0    /* c_has_sdout*/,
         0    /* c_has_sinit*/,
         0    /* c_has_sset*/,
         0    /* c_shift_type*/,
         "100000000000000"    /* c_sinit_val*/,
         0    /* c_sync_enable*/,
         0    /* c_sync_priority*/,
         15    /* c_width*/
      )
      BU565(
         .CLK(BU565_CLK),
         .SDIN(BU565_SDIN),
         .Q(BU565_Q),
         .CE(BU565_CE)
      );

      wire [3 : 0] BU598_I;
         assign BU598_I[0] = n1859;
         assign BU598_I[1] = n1860;
         assign BU598_I[2] = n1853;
         assign BU598_I[3] = n1857;
      wire BU598_T;
         assign BU598_T = 1'b0;
      wire BU598_EN;
         assign BU598_EN = 1'b0;
      wire BU598_Q;
      wire BU598_CLK;
         assign BU598_CLK = 1'b0;
      wire BU598_CE;
         assign BU598_CE = 1'b0;
      wire BU598_ACLR;
         assign BU598_ACLR = 1'b0;
      wire BU598_ASET;
         assign BU598_ASET = 1'b0;
      wire BU598_AINIT;
         assign BU598_AINIT = 1'b0;
      wire BU598_SCLR;
         assign BU598_SCLR = 1'b0;
      wire BU598_SSET;
         assign BU598_SSET = 1'b0;
      wire BU598_SINIT;
         assign BU598_SINIT = 1'b0;
      wire BU598_O;
         assign n1858 = BU598_O;
      C_GATE_BIT_V7_0 #(
         "0"    /* c_ainit_val*/,
         0    /* c_enable_rlocs*/,
         4    /* c_gate_type*/,
         0    /* c_has_aclr*/,
         0    /* c_has_ainit*/,
         0    /* c_has_aset*/,
         0    /* c_has_ce*/,
         1    /* c_has_o*/,
         1    /* c_has_q*/,
         0    /* c_has_sclr*/,
         0    /* c_has_sinit*/,
         0    /* c_has_sset*/,
         4    /* c_inputs*/,
         "0000"    /* c_input_inv_mask*/,
         0    /* c_pipe_stages*/,
         "0"    /* c_sinit_val*/,
         0    /* c_sync_enable*/,
         1    /* c_sync_priority*/
      )
      BU598(
         .I(BU598_I),
         .T(BU598_T),
         .EN(BU598_EN),
         .Q(BU598_Q),
         .CLK(BU598_CLK),
         .CE(BU598_CE),
         .ACLR(BU598_ACLR),
         .ASET(BU598_ASET),