ddsqam.v

基于FPGA的16QAM调制与解调的设计与实现源代码

         assign n896 = BU231_Q[18];
         assign n897 = BU231_Q[19];
         assign n898 = BU231_Q[20];
         assign n899 = BU231_Q[21];
         assign n900 = BU231_Q[22];
         assign n901 = BU231_Q[23];
         assign n902 = BU231_Q[24];
      wire BU231_CLK;
         assign BU231_CLK = n175;
      wire BU231_CE;
         assign BU231_CE = n19;
      C_REG_FD_V7_0 #(
         "0000000000000000000000000"    /* c_ainit_val*/,
         0    /* c_enable_rlocs*/,
         0    /* c_has_aclr*/,
         0    /* c_has_ainit*/,
         0    /* c_has_aset*/,
         1    /* c_has_ce*/,
         0    /* c_has_sclr*/,
         0    /* c_has_sinit*/,
         0    /* c_has_sset*/,
         "0000000000000000000000000"    /* c_sinit_val*/,
         0    /* c_sync_enable*/,
         0    /* c_sync_priority*/,
         25    /* c_width*/
      )
      BU231(
         .D(BU231_D),
         .Q(BU231_Q),
         .CLK(BU231_CLK),
         .CE(BU231_CE)
      );

      wire [24 : 0] BU283_A;
         assign BU283_A[0] = n36;
         assign BU283_A[1] = n37;
         assign BU283_A[2] = n38;
         assign BU283_A[3] = n39;
         assign BU283_A[4] = n40;
         assign BU283_A[5] = n41;
         assign BU283_A[6] = n42;
         assign BU283_A[7] = n43;
         assign BU283_A[8] = n44;
         assign BU283_A[9] = n45;
         assign BU283_A[10] = n46;
         assign BU283_A[11] = n47;
         assign BU283_A[12] = n48;
         assign BU283_A[13] = n49;
         assign BU283_A[14] = n50;
         assign BU283_A[15] = n51;
         assign BU283_A[16] = n52;
         assign BU283_A[17] = n53;
         assign BU283_A[18] = n54;
         assign BU283_A[19] = n55;
         assign BU283_A[20] = n56;
         assign BU283_A[21] = n57;
         assign BU283_A[22] = n58;
         assign BU283_A[23] = n59;
         assign BU283_A[24] = n60;
      wire [24 : 0] BU283_B;
         assign BU283_B[0] = n878;
         assign BU283_B[1] = n879;
         assign BU283_B[2] = n880;
         assign BU283_B[3] = n881;
         assign BU283_B[4] = n882;
         assign BU283_B[5] = n883;
         assign BU283_B[6] = n884;
         assign BU283_B[7] = n885;
         assign BU283_B[8] = n886;
         assign BU283_B[9] = n887;
         assign BU283_B[10] = n888;
         assign BU283_B[11] = n889;
         assign BU283_B[12] = n890;
         assign BU283_B[13] = n891;
         assign BU283_B[14] = n892;
         assign BU283_B[15] = n893;
         assign BU283_B[16] = n894;
         assign BU283_B[17] = n895;
         assign BU283_B[18] = n896;
         assign BU283_B[19] = n897;
         assign BU283_B[20] = n898;
         assign BU283_B[21] = n899;
         assign BU283_B[22] = n900;
         assign BU283_B[23] = n901;
         assign BU283_B[24] = n902;
      wire [24 : 0] BU283_Q;
         assign n63 = BU283_Q[2];
         assign n64 = BU283_Q[3];
         assign n65 = BU283_Q[4];
         assign n66 = BU283_Q[5];
         assign n67 = BU283_Q[6];
         assign n68 = BU283_Q[7];
         assign n69 = BU283_Q[8];
         assign n70 = BU283_Q[9];
         assign n71 = BU283_Q[10];
         assign n72 = BU283_Q[11];
         assign n73 = BU283_Q[12];
         assign n74 = BU283_Q[13];
         assign n75 = BU283_Q[14];
         assign n76 = BU283_Q[15];
         assign n77 = BU283_Q[16];
         assign n78 = BU283_Q[17];
         assign n79 = BU283_Q[18];
         assign n80 = BU283_Q[19];
         assign n81 = BU283_Q[20];
         assign n82 = BU283_Q[21];
         assign n83 = BU283_Q[22];
         assign n84 = BU283_Q[23];
         assign n85 = BU283_Q[24];
      wire BU283_CLK;
         assign BU283_CLK = n175;
      wire BU283_CE;
         assign BU283_CE = n176;
      C_ADDSUB_V7_0 #(
         0    /* c_add_mode*/,
         "0000000000000000000000000"    /* c_ainit_val*/,
         1    /* c_a_type*/,
         25    /* c_a_width*/,
         1    /* c_bypass_enable*/,
         0    /* c_bypass_low*/,
         0    /* c_b_constant*/,
         1    /* c_b_type*/,
         "0000000000000000000000000"    /* c_b_value*/,
         25    /* c_b_width*/,
         0    /* c_enable_rlocs*/,
         0    /* c_has_aclr*/,
         0    /* c_has_add*/,
         0    /* c_has_ainit*/,
         0    /* c_has_aset*/,
         0    /* c_has_a_signed*/,
         0    /* c_has_bypass*/,
         0    /* c_has_bypass_with_cin*/,
         0    /* c_has_b_in*/,
         0    /* c_has_b_out*/,
         0    /* c_has_b_signed*/,
         1    /* c_has_ce*/,
         0    /* c_has_c_in*/,
         0    /* c_has_c_out*/,
         0    /* c_has_ovfl*/,
         1    /* c_has_q*/,
         0    /* c_has_q_b_out*/,
         0    /* c_has_q_c_out*/,
         0    /* c_has_q_ovfl*/,
         1    /* c_has_s*/,
         0    /* c_has_sclr*/,
         0    /* c_has_sinit*/,
         0    /* c_has_sset*/,
         24    /* c_high_bit*/,
         1    /* c_latency*/,
         0    /* c_low_bit*/,
         25    /* c_out_width*/,
         0    /* c_pipe_stages*/,
         "0000000000000000000000000"    /* c_sinit_val*/,
         0    /* c_sync_enable*/,
         0    /* c_sync_priority*/
      )
      BU283(
         .A(BU283_A),
         .B(BU283_B),
         .Q(BU283_Q),
         .CLK(BU283_CLK),
         .CE(BU283_CE)
      );

      wire [22 : 0] BU752_A;
         assign BU752_A[0] = n63;
         assign BU752_A[1] = n64;
         assign BU752_A[2] = n65;
         assign BU752_A[3] = n66;
         assign BU752_A[4] = n67;
         assign BU752_A[5] = n68;
         assign BU752_A[6] = n69;
         assign BU752_A[7] = n70;
         assign BU752_A[8] = n71;
         assign BU752_A[9] = n72;
         assign BU752_A[10] = n73;
         assign BU752_A[11] = n74;
         assign BU752_A[12] = n75;
         assign BU752_A[13] = n76;
         assign BU752_A[14] = n77;
         assign BU752_A[15] = n78;
         assign BU752_A[16] = n79;
         assign BU752_A[17] = n80;
         assign BU752_A[18] = n81;
         assign BU752_A[19] = n82;
         assign BU752_A[20] = n83;
         assign BU752_A[21] = n84;
         assign BU752_A[22] = n85;
      wire [9 : 0] BU752_B;
         assign BU752_B[0] = n101;
         assign BU752_B[1] = n102;
         assign BU752_B[2] = n103;
         assign BU752_B[3] = n104;
         assign BU752_B[4] = n105;
         assign BU752_B[5] = n106;
         assign BU752_B[6] = n107;
         assign BU752_B[7] = n108;
         assign BU752_B[8] = n109;
         assign BU752_B[9] = n110;
      wire [13 : 0] BU752_Q;
         assign n87 = BU752_Q[0];
         assign n88 = BU752_Q[1];
         assign n89 = BU752_Q[2];
         assign n90 = BU752_Q[3];
         assign n91 = BU752_Q[4];
         assign n92 = BU752_Q[5];
         assign n93 = BU752_Q[6];
         assign n94 = BU752_Q[7];
         assign n95 = BU752_Q[8];
         assign n96 = BU752_Q[9];
         assign n97 = BU752_Q[10];
         assign n98 = BU752_Q[11];
         assign n99 = BU752_Q[12];
         assign n100 = BU752_Q[13];
      wire BU752_CLK;
         assign BU752_CLK = n175;
      wire BU752_CE;
         assign BU752_CE = n176;
      C_ADDSUB_V7_0 #(
         0    /* c_add_mode*/,
         "00000000000000"    /* c_ainit_val*/,
         1    /* c_a_type*/,
         23    /* c_a_width*/,
         1    /* c_bypass_enable*/,
         0    /* c_bypass_low*/,
         0    /* c_b_constant*/,
         0    /* c_b_type*/,
         "00000000000000000000000"    /* c_b_value*/,
         10    /* c_b_width*/,
         0    /* c_enable_rlocs*/,
         0    /* c_has_aclr*/,
         0    /* c_has_add*/,
         0    /* c_has_ainit*/,
         0    /* c_has_aset*/,
         0    /* c_has_a_signed*/,
         0    /* c_has_bypass*/,
         0    /* c_has_bypass_with_cin*/,
         0    /* c_has_b_in*/,
         0    /* c_has_b_out*/,
         0    /* c_has_b_signed*/,
         1    /* c_has_ce*/,
         0    /* c_has_c_in*/,
         0    /* c_has_c_out*/,
         0    /* c_has_ovfl*/,
         1    /* c_has_q*/,
         0    /* c_has_q_b_out*/,
         0    /* c_has_q_c_out*/,
         0    /* c_has_q_ovfl*/,
         1    /* c_has_s*/,
         0    /* c_has_sclr*/,
         0    /* c_has_sinit*/,
         0    /* c_has_sset*/,
         22    /* c_high_bit*/,
         1    /* c_latency*/,
         9    /* c_low_bit*/,
         14    /* c_out_width*/,
         0    /* c_pipe_stages*/,
         "00000000000000"    /* c_sinit_val*/,
         0    /* c_sync_enable*/,
         0    /* c_sync_priority*/
      )
      BU752(
         .A(BU752_A),
         .B(BU752_B),
         .Q(BU752_Q),
         .CLK(BU752_CLK),
         .CE(BU752_CE)
      );

      wire [8 : 0] BU691_A;
         assign BU691_A[0] = n1795;
         assign BU691_A[1] = n1796;
         assign BU691_A[2] = n1797;
         assign BU691_A[3] = n1798;
         assign BU691_A[4] = n1799;
         assign BU691_A[5] = n1800;
         assign BU691_A[6] = n1801;
         assign BU691_A[7] = n1802;
         assign BU691_A[8] = n1803;
      wire [8 : 0] BU691_B;
         assign BU691_B[0] = n1903;
         assign BU691_B[1] = n1904;
         assign BU691_B[2] = n1905;
         assign BU691_B[3] = n1906;
         assign BU691_B[4] = n1907;
         assign BU691_B[5] = n1908;
         assign BU691_B[6] = n1909;
         assign BU691_B[7] = n1910;
         assign BU691_B[8] = n1911;
      wire [9 : 0] BU691_Q;
         assign n101 = BU691_Q[0];
         assign n102 = BU691_Q[1];
         assign n103 = BU691_Q[2];
         assign n104 = BU691_Q[3];
         assign n105 = BU691_Q[4];
         assign n106 = BU691_Q[5];
         assign n107 = BU691_Q[6];
         assign n108 = BU691_Q[7];
         assign n109 = BU691_Q[8];
         assign n110 = BU691_Q[9];
      wire BU691_CLK;
         assign BU691_CLK = n175;
      wire BU691_CE;
         assign BU691_CE = n176;
      C_ADDSUB_V7_0 #(
         0    /* c_add_mode*/,
         "0000000000"    /* c_ainit_val*/,
         0    /* c_a_type*/,
         9    /* c_a_width*/,
         0    /* c_bypass_enable*/,
         0    /* c_bypass_low*/,
         0    /* c_b_constant*/,
         0    /* c_b_type*/,
         "0000000000"    /* c_b_value*/,
         9    /* c_b_width*/,
         0    /* c_enable_rlocs*/,
         0    /* c_has_aclr*/,
         0    /* c_has_add*/,
         0    /* c_has_ainit*/,
         0    /* c_has_aset*/,
         0    /* c_has_a_signed*/,
         0    /* c_has_bypass*/,
         0    /* c_has_bypass_with_cin*/,
         0    /* c_has_b_in*/,
         0    /* c_has_b_out*/,
         0    /* c_has_b_signed*/,
         1    /* c_has_ce*/,
         0    /* c_has_c_in*/,
         0    /* c_has_c_out*/,
         0    /* c_has_ovfl*/,
         1    /* c_has_q*/,
         0    /* c_has_q_b_out*/,
         0    /* c_has_q_c_out*/,
         0    /* c_has_q_ovfl*/,
         1    /* c_has_s*/,
         0    /* c_has_sclr*/,
         0    /* c_has_sinit*/,
         0    /* c_has_sset*/,
         9    /* c_high_bit*/,
         1    /* c_latency*/,
         0    /* c_low_bit*/,
         10    /* c_out_width*/,
         0    /* c_pipe_stages*/,
         "0000000000"    /* c_sinit_val*/,
         0    /* c_sync_enable*/,
         0    /* c_sync_priority*/
      )
      BU691(
         .A(BU691_A),
         .B(BU691_B),
         .Q(BU691_Q),
         .CLK(BU691_CLK),
         .CE(BU691_CE)
      );

      wire [7 : 0] BU505_A;
         assign BU505_A[0] = n1694;
         assign BU505_A[1] = n1695;
         assign BU505_A[2] = n1696;
         assign BU505_A[3] = n1697;
         assign BU505_A[4] = n1698;
         assign BU505_A[5] = n1699;
         assign BU505_A[6] = n1700;
         assign BU505_A[7] = n1701;
      wire [7 : 0] BU505_B;
         assign BU505_B[0] = n1744;
         assign BU505_B[1] = n1745;
         assign BU505_B[2] = n1746;
         assign BU505_B[3] = n1747;
         assign BU505_B[4] = n1748;
         assign BU505_B[5] = n1749;
         assign BU505_B[6] = n1750;
         assign BU505_B[7] = n1751;
      wire [8 : 0] BU505_Q;
         assign n1795 = BU505_Q[0];
         assign n1796 = BU505_Q[1];
         assign n1797 = BU505_Q[2];
         assign n1798 = BU505_Q[3];
         assign n1799 = BU505_Q[4];
         assign n1800 = BU505_Q[5];
         assign n1801 = BU505_Q[6];
         assign n1802 = BU505_Q[7];
         assign n1803 = BU505_Q[8];
      wire BU505_CLK;
         assign BU505_CLK = n175;
      wire BU505_CE;
         assign BU505_CE = n176;
      C_ADDSUB_V7_0 #(
         0    /* c_add_mode*/,
         "000000000"    /* c_ainit_val*/,
         0    /* c_a_type*/,
         8    /* c_a_width*/,
         0    /* c_bypass_enable*/,
         0    /* c_bypass_low*/,
         0    /* c_b_constant*/,
         0    /* c_b_type*/,
         "000000000"    /* c_b_value*/,
         8    /* c_b_width*/,
         0    /* c_enable_rlocs*/,
         0    /* c_has_aclr*/,
         0    /* c_has_add*/,
         0    /* c_has_ainit*/,
         0    /* c_has_aset*/,
         0    /* c_has_a_signed*/,
         0    /* c_has_bypass*/,
         0    /* c_has_bypass_with_cin*/,
         0    /* c_has_b_in*/,
         0    /* c_has_b_out*/,
         0    /* c_has_b_signed*/,
         1    /* c_has_ce*/,
         0    /* c_has_c_in*/,
         0    /* c_has_c_out*/,
         0    /* c_has_ovfl*/,
         1    /* c_has_q*/,
         0    /* c_has_q_b_out*/,
         0    /* c_has_q_c_out*/,
         0    /* c_has_q_ovfl*/,
         1    /* c_has_s*/,
         0    /* c_has_sclr*/,
         0    /* c_has_sinit*/,
         0    /* c_has_sset*/,
         8    /* c_high_bit*/,
         1    /* c_latency*/,
         0    /* c_low_bit*/,
         9    /* c_out_width*/,
         0    /* c_pipe_stages*/,
         "000000000"    /* c_sinit_val*/,
         0    /* c_sync_enable*/,
         0    /* c_sync_priority*/
      )
      BU505(
         .A(BU505_A),
         .B(BU505_B),
         .Q(BU505_Q),
         .CLK(BU505_CLK),
         .CE(BU505_CE)
      );

      wire [3 : 0] BU436_I;
         assign BU436_I[0] = n1703;
         assign BU436_I[1] = n1704;
         assign BU436_I[2] = n1705;
         assign BU436_I[3] = n1701;
      wire BU436_T;
         assign BU436_T = 1'b0;
      wire BU436_EN;
         assign BU436_EN = 1'b0;
      wire BU436_Q;
      wire BU436_CLK;
         assign BU436_CLK = 1'b0;
      wire BU436_CE;
         assign BU436_CE = 1'b0;
      wire BU436_ACLR;