ddsqam.v

基于FPGA的16QAM调制与解调的设计与实现源代码

   assign SINE[2] = n179;
   assign SINE[3] = n180;
   assign SINE[4] = n181;
   assign SINE[5] = n182;
   assign SINE[6] = n183;
   assign SINE[7] = n184;
   assign SINE[8] = n185;
   assign SINE[9] = n186;
   assign SINE[10] = n187;
   assign SINE[11] = n188;
   assign SINE[12] = n189;
   assign SINE[13] = n190;
   assign SINE[14] = n191;
   assign SINE[15] = n192;
   assign COSINE[0] = n193;
   assign COSINE[1] = n194;
   assign COSINE[2] = n195;
   assign COSINE[3] = n196;
   assign COSINE[4] = n197;
   assign COSINE[5] = n198;
   assign COSINE[6] = n199;
   assign COSINE[7] = n200;
   assign COSINE[8] = n201;
   assign COSINE[9] = n202;
   assign COSINE[10] = n203;
   assign COSINE[11] = n204;
   assign COSINE[12] = n205;
   assign COSINE[13] = n206;
   assign COSINE[14] = n207;
   assign COSINE[15] = n208;

      wire [5 : 0] BU2_I;
         assign BU2_I[0] = n20;
         assign BU2_I[1] = n21;
         assign BU2_I[2] = n22;
         assign BU2_I[3] = n23;
         assign BU2_I[4] = n24;
         assign BU2_I[5] = n25;
      wire BU2_T;
         assign BU2_T = 1'b0;
      wire BU2_EN;
         assign BU2_EN = 1'b0;
      wire BU2_Q;
      wire BU2_CLK;
         assign BU2_CLK = 1'b0;
      wire BU2_CE;
         assign BU2_CE = 1'b0;
      wire BU2_ACLR;
         assign BU2_ACLR = 1'b0;
      wire BU2_ASET;
         assign BU2_ASET = 1'b0;
      wire BU2_AINIT;
         assign BU2_AINIT = 1'b0;
      wire BU2_SCLR;
         assign BU2_SCLR = 1'b0;
      wire BU2_SSET;
         assign BU2_SSET = 1'b0;
      wire BU2_SINIT;
         assign BU2_SINIT = 1'b0;
      wire BU2_O;
         assign n2 = BU2_O;
      C_GATE_BIT_V7_0 #(
         "0"    /* c_ainit_val*/,
         0    /* c_enable_rlocs*/,
         0    /* c_gate_type*/,
         0    /* c_has_aclr*/,
         0    /* c_has_ainit*/,
         0    /* c_has_aset*/,
         0    /* c_has_ce*/,
         1    /* c_has_o*/,
         1    /* c_has_q*/,
         0    /* c_has_sclr*/,
         0    /* c_has_sinit*/,
         0    /* c_has_sset*/,
         6    /* c_inputs*/,
         "011111"    /* c_input_inv_mask*/,
         0    /* c_pipe_stages*/,
         "0"    /* c_sinit_val*/,
         0    /* c_sync_enable*/,
         1    /* c_sync_priority*/
      )
      BU2(
         .I(BU2_I),
         .T(BU2_T),
         .EN(BU2_EN),
         .Q(BU2_Q),
         .CLK(BU2_CLK),
         .CE(BU2_CE),
         .ACLR(BU2_ACLR),
         .ASET(BU2_ASET),
         .AINIT(BU2_AINIT),
         .SCLR(BU2_SCLR),
         .SSET(BU2_SSET),
         .SINIT(BU2_SINIT),
         .O(BU2_O)
      );

      wire [5 : 0] BU10_I;
         assign BU10_I[0] = n20;
         assign BU10_I[1] = n21;
         assign BU10_I[2] = n22;
         assign BU10_I[3] = n23;
         assign BU10_I[4] = n24;
         assign BU10_I[5] = n25;
      wire BU10_T;
         assign BU10_T = 1'b0;
      wire BU10_EN;
         assign BU10_EN = 1'b0;
      wire BU10_Q;
      wire BU10_CLK;
         assign BU10_CLK = 1'b0;
      wire BU10_CE;
         assign BU10_CE = 1'b0;
      wire BU10_ACLR;
         assign BU10_ACLR = 1'b0;
      wire BU10_ASET;
         assign BU10_ASET = 1'b0;
      wire BU10_AINIT;
         assign BU10_AINIT = 1'b0;
      wire BU10_SCLR;
         assign BU10_SCLR = 1'b0;
      wire BU10_SSET;
         assign BU10_SSET = 1'b0;
      wire BU10_SINIT;
         assign BU10_SINIT = 1'b0;
      wire BU10_O;
         assign n19 = BU10_O;
      C_GATE_BIT_V7_0 #(
         "0"    /* c_ainit_val*/,
         0    /* c_enable_rlocs*/,
         0    /* c_gate_type*/,
         0    /* c_has_aclr*/,
         0    /* c_has_ainit*/,
         0    /* c_has_aset*/,
         0    /* c_has_ce*/,
         1    /* c_has_o*/,
         1    /* c_has_q*/,
         0    /* c_has_sclr*/,
         0    /* c_has_sinit*/,
         0    /* c_has_sset*/,
         6    /* c_inputs*/,
         "001111"    /* c_input_inv_mask*/,
         0    /* c_pipe_stages*/,
         "0"    /* c_sinit_val*/,
         0    /* c_sync_enable*/,
         1    /* c_sync_priority*/
      )
      BU10(
         .I(BU10_I),
         .T(BU10_T),
         .EN(BU10_EN),
         .Q(BU10_Q),
         .CLK(BU10_CLK),
         .CE(BU10_CE),
         .ACLR(BU10_ACLR),
         .ASET(BU10_ASET),
         .AINIT(BU10_AINIT),
         .SCLR(BU10_SCLR),
         .SSET(BU10_SSET),
         .SINIT(BU10_SINIT),
         .O(BU10_O)
      );

      wire [24 : 0] BU20_D;
         assign BU20_D[0] = n144;
         assign BU20_D[1] = n145;
         assign BU20_D[2] = n146;
         assign BU20_D[3] = n147;
         assign BU20_D[4] = n148;
         assign BU20_D[5] = n149;
         assign BU20_D[6] = n150;
         assign BU20_D[7] = n151;
         assign BU20_D[8] = n152;
         assign BU20_D[9] = n153;
         assign BU20_D[10] = n154;
         assign BU20_D[11] = n155;
         assign BU20_D[12] = n156;
         assign BU20_D[13] = n157;
         assign BU20_D[14] = n158;
         assign BU20_D[15] = n159;
         assign BU20_D[16] = n160;
         assign BU20_D[17] = n161;
         assign BU20_D[18] = n162;
         assign BU20_D[19] = n163;
         assign BU20_D[20] = n164;
         assign BU20_D[21] = n165;
         assign BU20_D[22] = n166;
         assign BU20_D[23] = n167;
         assign BU20_D[24] = n168;
      wire [24 : 0] BU20_Q;
         assign n282 = BU20_Q[0];
         assign n283 = BU20_Q[1];
         assign n284 = BU20_Q[2];
         assign n285 = BU20_Q[3];
         assign n286 = BU20_Q[4];
         assign n287 = BU20_Q[5];
         assign n288 = BU20_Q[6];
         assign n289 = BU20_Q[7];
         assign n290 = BU20_Q[8];
         assign n291 = BU20_Q[9];
         assign n292 = BU20_Q[10];
         assign n293 = BU20_Q[11];
         assign n294 = BU20_Q[12];
         assign n295 = BU20_Q[13];
         assign n296 = BU20_Q[14];
         assign n297 = BU20_Q[15];
         assign n298 = BU20_Q[16];
         assign n299 = BU20_Q[17];
         assign n300 = BU20_Q[18];
         assign n301 = BU20_Q[19];
         assign n302 = BU20_Q[20];
         assign n303 = BU20_Q[21];
         assign n304 = BU20_Q[22];
         assign n305 = BU20_Q[23];
         assign n306 = BU20_Q[24];
      wire BU20_CLK;
         assign BU20_CLK = n175;
      wire BU20_CE;
         assign BU20_CE = n2;
      C_REG_FD_V7_0 #(
         "0001010001111010111000011"    /* c_ainit_val*/,
         0    /* c_enable_rlocs*/,
         0    /* c_has_aclr*/,
         0    /* c_has_ainit*/,
         0    /* c_has_aset*/,
         1    /* c_has_ce*/,
         0    /* c_has_sclr*/,
         0    /* c_has_sinit*/,
         0    /* c_has_sset*/,
         "0000000000000000000000000"    /* c_sinit_val*/,
         0    /* c_sync_enable*/,
         0    /* c_sync_priority*/,
         25    /* c_width*/
      )
      BU20(
         .D(BU20_D),
         .Q(BU20_Q),
         .CLK(BU20_CLK),
         .CE(BU20_CE)
      );

      wire [24 : 0] BU72_A;
         assign BU72_A[0] = n36;
         assign BU72_A[1] = n37;
         assign BU72_A[2] = n38;
         assign BU72_A[3] = n39;
         assign BU72_A[4] = n40;
         assign BU72_A[5] = n41;
         assign BU72_A[6] = n42;
         assign BU72_A[7] = n43;
         assign BU72_A[8] = n44;
         assign BU72_A[9] = n45;
         assign BU72_A[10] = n46;
         assign BU72_A[11] = n47;
         assign BU72_A[12] = n48;
         assign BU72_A[13] = n49;
         assign BU72_A[14] = n50;
         assign BU72_A[15] = n51;
         assign BU72_A[16] = n52;
         assign BU72_A[17] = n53;
         assign BU72_A[18] = n54;
         assign BU72_A[19] = n55;
         assign BU72_A[20] = n56;
         assign BU72_A[21] = n57;
         assign BU72_A[22] = n58;
         assign BU72_A[23] = n59;
         assign BU72_A[24] = n60;
      wire [24 : 0] BU72_B;
         assign BU72_B[0] = n282;
         assign BU72_B[1] = n283;
         assign BU72_B[2] = n284;
         assign BU72_B[3] = n285;
         assign BU72_B[4] = n286;
         assign BU72_B[5] = n287;
         assign BU72_B[6] = n288;
         assign BU72_B[7] = n289;
         assign BU72_B[8] = n290;
         assign BU72_B[9] = n291;
         assign BU72_B[10] = n292;
         assign BU72_B[11] = n293;
         assign BU72_B[12] = n294;
         assign BU72_B[13] = n295;
         assign BU72_B[14] = n296;
         assign BU72_B[15] = n297;
         assign BU72_B[16] = n298;
         assign BU72_B[17] = n299;
         assign BU72_B[18] = n300;
         assign BU72_B[19] = n301;
         assign BU72_B[20] = n302;
         assign BU72_B[21] = n303;
         assign BU72_B[22] = n304;
         assign BU72_B[23] = n305;
         assign BU72_B[24] = n306;
      wire [24 : 0] BU72_Q;
         assign n36 = BU72_Q[0];
         assign n37 = BU72_Q[1];
         assign n38 = BU72_Q[2];
         assign n39 = BU72_Q[3];
         assign n40 = BU72_Q[4];
         assign n41 = BU72_Q[5];
         assign n42 = BU72_Q[6];
         assign n43 = BU72_Q[7];
         assign n44 = BU72_Q[8];
         assign n45 = BU72_Q[9];
         assign n46 = BU72_Q[10];
         assign n47 = BU72_Q[11];
         assign n48 = BU72_Q[12];
         assign n49 = BU72_Q[13];
         assign n50 = BU72_Q[14];
         assign n51 = BU72_Q[15];
         assign n52 = BU72_Q[16];
         assign n53 = BU72_Q[17];
         assign n54 = BU72_Q[18];
         assign n55 = BU72_Q[19];
         assign n56 = BU72_Q[20];
         assign n57 = BU72_Q[21];
         assign n58 = BU72_Q[22];
         assign n59 = BU72_Q[23];
         assign n60 = BU72_Q[24];
      wire BU72_CLK;
         assign BU72_CLK = n175;
      wire BU72_CE;
         assign BU72_CE = n176;
      C_ADDSUB_V7_0 #(
         0    /* c_add_mode*/,
         "0000000000000000000000000"    /* c_ainit_val*/,
         1    /* c_a_type*/,
         25    /* c_a_width*/,
         1    /* c_bypass_enable*/,
         0    /* c_bypass_low*/,
         0    /* c_b_constant*/,
         1    /* c_b_type*/,
         "0000000000000000000000000"    /* c_b_value*/,
         25    /* c_b_width*/,
         0    /* c_enable_rlocs*/,
         0    /* c_has_aclr*/,
         0    /* c_has_add*/,
         0    /* c_has_ainit*/,
         0    /* c_has_aset*/,
         0    /* c_has_a_signed*/,
         0    /* c_has_bypass*/,
         0    /* c_has_bypass_with_cin*/,
         0    /* c_has_b_in*/,
         0    /* c_has_b_out*/,
         0    /* c_has_b_signed*/,
         1    /* c_has_ce*/,
         0    /* c_has_c_in*/,
         0    /* c_has_c_out*/,
         0    /* c_has_ovfl*/,
         1    /* c_has_q*/,
         0    /* c_has_q_b_out*/,
         0    /* c_has_q_c_out*/,
         0    /* c_has_q_ovfl*/,
         1    /* c_has_s*/,
         0    /* c_has_sclr*/,
         0    /* c_has_sinit*/,
         0    /* c_has_sset*/,
         24    /* c_high_bit*/,
         1    /* c_latency*/,
         0    /* c_low_bit*/,
         25    /* c_out_width*/,
         0    /* c_pipe_stages*/,
         "0000000000000000000000000"    /* c_sinit_val*/,
         0    /* c_sync_enable*/,
         0    /* c_sync_priority*/
      )
      BU72(
         .A(BU72_A),
         .B(BU72_B),
         .Q(BU72_Q),
         .CLK(BU72_CLK),
         .CE(BU72_CE)
      );

      wire BU222_CLK;
         assign BU222_CLK = n175;
      wire BU222_SDOUT;
         assign n86 = BU222_SDOUT;
      wire BU222_CE;
         assign BU222_CE = n176;
      C_SHIFT_FD_V7_0 #(
         "00"    /* c_ainit_val*/,
         0    /* c_enable_rlocs*/,
         1    /* c_fill_data*/,
         0    /* c_has_aclr*/,
         0    /* c_has_ainit*/,
         0    /* c_has_aset*/,
         1    /* c_has_ce*/,
         0    /* c_has_d*/,
         0    /* c_has_lsb_2_msb*/,
         0    /* c_has_q*/,
         0    /* c_has_sclr*/,
         0    /* c_has_sdin*/,
         1    /* c_has_sdout*/,
         0    /* c_has_sinit*/,
         0    /* c_has_sset*/,
         1    /* c_shift_type*/,
         "00"    /* c_sinit_val*/,
         0    /* c_sync_enable*/,
         1    /* c_sync_priority*/,
         2    /* c_width*/
      )
      BU222(
         .CLK(BU222_CLK),
         .SDOUT(BU222_SDOUT),
         .CE(BU222_CE)
      );

      wire [24 : 0] BU231_D;
         assign BU231_D[0] = n144;
         assign BU231_D[1] = n145;
         assign BU231_D[2] = n146;
         assign BU231_D[3] = n147;
         assign BU231_D[4] = n148;
         assign BU231_D[5] = n149;
         assign BU231_D[6] = n150;
         assign BU231_D[7] = n151;
         assign BU231_D[8] = n152;
         assign BU231_D[9] = n153;
         assign BU231_D[10] = n154;
         assign BU231_D[11] = n155;
         assign BU231_D[12] = n156;
         assign BU231_D[13] = n157;
         assign BU231_D[14] = n158;
         assign BU231_D[15] = n159;
         assign BU231_D[16] = n160;
         assign BU231_D[17] = n161;
         assign BU231_D[18] = n162;
         assign BU231_D[19] = n163;
         assign BU231_D[20] = n164;
         assign BU231_D[21] = n165;
         assign BU231_D[22] = n166;
         assign BU231_D[23] = n167;
         assign BU231_D[24] = n168;
      wire [24 : 0] BU231_Q;
         assign n878 = BU231_Q[0];
         assign n879 = BU231_Q[1];
         assign n880 = BU231_Q[2];
         assign n881 = BU231_Q[3];
         assign n882 = BU231_Q[4];
         assign n883 = BU231_Q[5];
         assign n884 = BU231_Q[6];
         assign n885 = BU231_Q[7];
         assign n886 = BU231_Q[8];
         assign n887 = BU231_Q[9];
         assign n888 = BU231_Q[10];
         assign n889 = BU231_Q[11];
         assign n890 = BU231_Q[12];
         assign n891 = BU231_Q[13];
         assign n892 = BU231_Q[14];
         assign n893 = BU231_Q[15];
         assign n894 = BU231_Q[16];
         assign n895 = BU231_Q[17];