fir.vhd

fir滤波器程序的实现

--===========================================================================--
--                                                                           --
--  S Y N T H E S I Z A B L E    FIR filter   C O R E                        --
--                                                                           --
--  www.opencores.org - January 2000                                         --
--  This IP core adheres to the GNU public license.                          --
--                                                                           --
--  VHDL model of Finite Impulse Response filter                             --
--                                                                           --
--  This model uses dual-port memory for storing coefficients and samples.   --
--  Resolution of coefficients and samples is adjustable. Number of TAPs     --
--  depends on dual-port memory size. This design can be cascaded to         --
--  form FIR filter with even greater number of TAPS.                        --
--                                                                           --
--  Implementation with 16x16 bit fixed point multiplier in Xilinx Virtex    --
--  XCV50-6 runs at 55 MHz and with 256 TAPs can handle frequency            --
--  bandwidth of +-107KHz.                                                   --
--                                                                           --
--  Author: Damjan Lampret, [e-mail]                            --
--                                                                           --
--  TO DO:                                                                   --
--                                                                           --
--   - synthesis with Syplify pending (there are some problems with          --
--     UNSIGNED and BIT_LOGIC_VECTOR types in some units !)                  --
--                                                                           --
--   - testbench                                                             --
--                                                                           --
--   - support for more dual-port memories (currently supported              --
--     Virtex/Spartan2 (generic dual-port memory added but not tested))      --
--                                                                           --
--   - top level "cascade" module for easy cascading several FIR filters     --
--                                                                           --
--   - verification with real application and real coefficients              --
--                                                                           --
--===========================================================================--

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.config.all;

entity fir is
    port (
    	CLK: in STD_LOGIC;
    	RST: in STD_LOGIC;
    	LOADING_COEFF: out STD_LOGIC;
    	OUTPUT_VALID: out STD_LOGIC;
    	INPUT: in STD_LOGIC_VECTOR (INPUT_WIDTH-1 downto 0);
        OUTPUT: out STD_LOGIC_VECTOR (OUTPUT_WIDTH-1 downto 0)
    );
end fir;

architecture fir_arch of fir is

component sample_dpmem
    port (
	INPUT  : in STD_LOGIC_VECTOR (INPUT_WIDTH-1 downto 0);
	OUTPUT : out STD_LOGIC_VECTOR (INPUT_WIDTH-1 downto 0);
	ADDNEW : in STD_LOGIC;
	CLK : in STD_LOGIC;
	RST : in STD_LOGIC
    );
end component;

component coeff_dpmem
    port (
	INPUT  : in STD_LOGIC_VECTOR (COEFF_WIDTH-1 downto 0);
	OUTPUT : out STD_LOGIC_VECTOR (COEFF_WIDTH-1 downto 0);
	REPEAT : out STD_LOGIC;
	LOADING_COEFF : out STD_LOGIC;
	CLK : in STD_LOGIC;
	RST : in STD_LOGIC
    );
end component;

component mac
    port (
	COEFF_IN  : in STD_LOGIC_VECTOR (COEFF_WIDTH-1 downto 0);
	SAMPLE_IN : in STD_LOGIC_VECTOR (INPUT_WIDTH-1 downto 0);
	OUTPUT : out STD_LOGIC_VECTOR (COEFF_WIDTH+INPUT_WIDTH+TAPS-1 downto 0);
	RESTART  : in STD_LOGIC;
	CLK : in STD_LOGIC;
	RST : in STD_LOGIC
    );
end component;

signal COEFF: STD_LOGIC_VECTOR (COEFF_WIDTH-1 downto 0);
signal SAMPLE: STD_LOGIC_VECTOR (INPUT_WIDTH-1 downto 0);
signal MAC_OUT: STD_LOGIC_VECTOR (COEFF_WIDTH+INPUT_WIDTH+TAPS-1 downto 0);
signal CYCLE: STD_LOGIC;
signal DELAYED_RESTART: STD_LOGIC;

begin

sample_dpmem_inst: sample_dpmem
    port map (
	INPUT(INPUT_WIDTH-1 downto 0) => INPUT(INPUT_WIDTH-1 downto 0),
	OUTPUT => SAMPLE,
	ADDNEW => CYCLE,
	CLK => CLK,
	RST => RST
    );

coeff_dpmem_inst: coeff_dpmem
    port map (
	INPUT(COEFF_WIDTH-1 downto 0) => INPUT(COEFF_WIDTH-1 downto 0),
	OUTPUT => COEFF,
	REPEAT => CYCLE,
	LOADING_COEFF => LOADING_COEFF,
	CLK => CLK,
	RST => RST
    );

mac_inst: mac
    port map (
    	COEFF_IN => COEFF,
    	SAMPLE_IN => SAMPLE,
    	OUTPUT => MAC_OUT,
    	RESTART => DELAYED_RESTART,
    	CLK => CLK,
    	RST => RST
    );

OUTPUT <= MAC_OUT(COEFF_WIDTH+INPUT_WIDTH+TAPS-1 downto COEFF_WIDTH+INPUT_WIDTH+TAPS-OUTPUT_WIDTH);
OUTPUT_VALID <= CYCLE;

output_delay:
process(CLK,RST,CYCLE)
variable counter: INTEGER range 2 downto 0;
begin
	if RST = '1' or CYCLE = '1' then
		DELAYED_RESTART <= '0';
		counter := 0;
	elsif rising_edge(CLK) then
		if counter < 1 then
			counter := counter + 1;
		elsif counter = 1 then
			DELAYED_RESTART <= '1';
			counter := 2;
		else
			DELAYED_RESTART <= '0';
		end if;
	end if;
end process;

end fir_arch;