config.vhd

fir滤波器程序的实现

--===========================================================================--
--                                                                           --
--  S Y N T H E S I Z A B L E    FIR filter   C O R E                        --
--                                                                           --
--  www.opencores.org - January 2000                                         --
--  This IP core adheres to the GNU public license.                          --
--                                                                           --
--  VHDL model of Finite Impulse Response filter                             --
--                                                                           --
--  This model uses dual-port memory for storing coefficients and samples.   --
--  Resolution of coefficients and samples is adjustable. Number of TAPs     --
--  depends on dual-port memory size. This design can be cascaded to         --
--  form FIR filter with even greater number of TAPS.                        --
--                                                                           --
--  Implementation with 16x16 bit fixed point multiplier in Xilinx Virtex    --
--  XCV50-6 runs at 55 MHz and with 256 TAPs can handle frequency            --
--  bandwidth of +-107KHz.                                                   --
--                                                                           --
--  Author: Damjan Lampret, [e-mail]                            --
--                                                                           --
--  TO DO:                                                                   --
--                                                                           --
--   - synthesis with Syplify pending (there are some problems with          --
--     UNSIGNED and BIT_LOGIC_VECTOR types in some units !)                  --
--                                                                           --
--   - testbench                                                             --
--                                                                           --
--   - support for more dual-port memories (currently supported              --
--     Virtex/Spartan2 (generic dual-port memory added but not tested))      --
--                                                                           --
--   - top level "cascade" module for easy cascading several FIR filters     --
--                                                                           --
--   - verification with real application and real coefficients              --
--                                                                           --
--===========================================================================--

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.math_real.all;

package CONFIG is
	
	-- User changable FIR parameters

	-- Number of TAPs. It should be less or equal to 2^TAPS.
	constant NUM_TAPS	: INTEGER	:= 12;

	-- Number of bits for TAP counter. Log2(NUM_TAPS)+1
	constant TAPS		: INTEGER	:= 4;
	
	-- Width of coefficients (default is 16 bits). It should be less or equal to MAXMEMWIDTH.
	constant COEFF_WIDTH	: INTEGER	:= 16;
	
	-- Width of input samples (default is 16 bits). It should be less or equal to MAXMEMWIDTH.
	constant INPUT_WIDTH	: INTEGER	:= 16;
	
	-- Width of filter output (default is 16 bits). It should be less or equal to MAXMEMWIDTH.
	constant OUTPUT_WIDTH	: INTEGER	:= 36;
	
	-- Set to 1 if coefficients are already loaded at startup otherwise 0.
	constant COEFF_LOADED_AT_STARTUP	: STD_LOGIC	:= '0';

	-- DON'T CHANGE BELOW UNLESS YOU KNOW WHAT YOU ARE DOING

	-- Maximum data width of memory components (16 for Virtex RAMB4_S16_S16 component)
	constant MAXMEMWIDTH	: INTEGER	:= 16;

	-- Maximum address space of memory components (8 for 256 words of Virtex RAMB4_S16_S16 BlockRAM)
	constant MAXMEMADDR	: INTEGER	:= 8;

	-- Convert SIGNED type to STD_LOGIC_VECTOR type
	function MAKE_BINARY(A : SIGNED) return STD_LOGIC_VECTOR;
	
end CONFIG;

package body CONFIG is

   -- synopsys synthesis_off
    type tbl_type is array (STD_ULOGIC) of STD_ULOGIC;
    constant tbl_BINARY : tbl_type :=
	('X', 'X', '0', '1', 'X', 'X', '0', '1', 'X');
    -- synopsys synthesis_on

    function MAKE_BINARY(A : SIGNED) return STD_LOGIC_VECTOR is
	-- synopsys built_in SYN_FEED_THRU
	variable one_bit : STD_ULOGIC;
	variable result : STD_LOGIC_VECTOR (A'range);
    begin
	-- synopsys synthesis_off
	    for i in A'range loop
	        if (IS_X(A(i))) then
		    result := (others => 'X');
	            return result;
	        end if;
		result(i) := tbl_BINARY(A(i));
	    end loop;
	    return result;
	-- synopsys synthesis_on
    end;
    
end CONFIG;